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system(h7): update STM32H7xx CMSIS Drivers to v1.10.7
Included in STM32CubeH7 FW v1.13.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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Lines changed: 593 additions & 508 deletions

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‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -11942,38 +11942,38 @@ typedef struct
1194211942
#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
1194311943
#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
1194411944

11945-
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po
11946-
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms
11945+
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
11946+
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
1194711947
#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
1194811948
#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
1194911949
#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
1195011950

11951-
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po
11952-
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms
11951+
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
11952+
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
1195311953
#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
1195411954
#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
1195511955
#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
1195611956

11957-
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po
11958-
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms
11957+
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
11958+
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
1195911959
#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
1196011960
#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
1196111961
#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
1196211962

11963-
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po
11964-
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms
11963+
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
11964+
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
1196511965
#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
1196611966
#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
1196711967
#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
1196811968

11969-
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po
11970-
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms
11969+
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
11970+
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
1197111971
#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
1197211972
#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
1197311973
#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
1197411974

11975-
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po
11976-
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms
11975+
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
11976+
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
1197711977
#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
1197811978
#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
1197911979
#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
@@ -16452,10 +16452,10 @@ typedef struct
1645216452
#define RNG_CR_CLKDIV_Pos (16U)
1645316453
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
1645416454
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
16455-
#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16456-
#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16457-
#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16458-
#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
16455+
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16456+
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16457+
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16458+
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
1645916459
#define RNG_CR_RNG_CONFIG1_Pos (20U)
1646016460
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
1646116461
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
@@ -19893,7 +19893,7 @@ typedef struct
1989319893

1989419894
/******************* Bit definition for TIM_CCR5 register *******************/
1989519895
#define TIM_CCR5_CCR5_Pos (0U)
19896-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
19896+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1989719897
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1989819898
#define TIM_CCR5_GC5C1_Pos (29U)
1989919899
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -23694,7 +23694,7 @@ typedef struct
2369423694

2369523695
/******************************** HSEM Instances *******************************/
2369623696
#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
23697-
#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
23697+
#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */
2369823698
#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2369923699
#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2370023700

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -11943,38 +11943,38 @@ typedef struct
1194311943
#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
1194411944
#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
1194511945

11946-
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po
11947-
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms
11946+
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
11947+
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
1194811948
#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
1194911949
#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
1195011950
#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
1195111951

11952-
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po
11953-
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms
11952+
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
11953+
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
1195411954
#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
1195511955
#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
1195611956
#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
1195711957

11958-
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po
11959-
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms
11958+
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
11959+
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
1196011960
#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
1196111961
#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
1196211962
#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
1196311963

11964-
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po
11965-
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms
11964+
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
11965+
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
1196611966
#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
1196711967
#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
1196811968
#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
1196911969

11970-
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po
11971-
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms
11970+
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
11971+
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
1197211972
#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
1197311973
#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
1197411974
#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
1197511975

11976-
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po
11977-
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms
11976+
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
11977+
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
1197811978
#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
1197911979
#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
1198011980
#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
@@ -16464,10 +16464,10 @@ typedef struct
1646416464
#define RNG_CR_CLKDIV_Pos (16U)
1646516465
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
1646616466
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
16467-
#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16468-
#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16469-
#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16470-
#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
16467+
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16468+
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16469+
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16470+
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
1647116471
#define RNG_CR_RNG_CONFIG1_Pos (20U)
1647216472
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
1647316473
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
@@ -19905,7 +19905,7 @@ typedef struct
1990519905

1990619906
/******************* Bit definition for TIM_CCR5 register *******************/
1990719907
#define TIM_CCR5_CCR5_Pos (0U)
19908-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
19908+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1990919909
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1991019910
#define TIM_CCR5_GC5C1_Pos (29U)
1991119911
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -23706,7 +23706,7 @@ typedef struct
2370623706

2370723707
/******************************** HSEM Instances *******************************/
2370823708
#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
23709-
#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
23709+
#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */
2371023710
#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2371123711
#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2371223712

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -12196,38 +12196,38 @@ typedef struct
1219612196
#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
1219712197
#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
1219812198

12199-
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po
12200-
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms
12199+
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
12200+
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
1220112201
#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
1220212202
#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
1220312203
#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
1220412204

12205-
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po
12206-
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms
12205+
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
12206+
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
1220712207
#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
1220812208
#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
1220912209
#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
1221012210

12211-
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po
12212-
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms
12211+
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
12212+
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
1221312213
#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
1221412214
#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
1221512215
#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
1221612216

12217-
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po
12218-
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms
12217+
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
12218+
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
1221912219
#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
1222012220
#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
1222112221
#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
1222212222

12223-
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po
12224-
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms
12223+
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
12224+
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
1222512225
#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
1222612226
#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
1222712227
#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
1222812228

12229-
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po
12230-
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms
12229+
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
12230+
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
1223112231
#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
1223212232
#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
1223312233
#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
@@ -16939,10 +16939,10 @@ typedef struct
1693916939
#define RNG_CR_CLKDIV_Pos (16U)
1694016940
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
1694116941
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
16942-
#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16943-
#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16944-
#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16945-
#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
16942+
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16943+
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16944+
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16945+
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
1694616946
#define RNG_CR_RNG_CONFIG1_Pos (20U)
1694716947
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
1694816948
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
@@ -20380,7 +20380,7 @@ typedef struct
2038020380

2038120381
/******************* Bit definition for TIM_CCR5 register *******************/
2038220382
#define TIM_CCR5_CCR5_Pos (0U)
20383-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
20383+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
2038420384
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
2038520385
#define TIM_CCR5_GC5C1_Pos (29U)
2038620386
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -24185,7 +24185,7 @@ typedef struct
2418524185

2418624186
/******************************** HSEM Instances *******************************/
2418724187
#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
24188-
#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
24188+
#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */
2418924189
#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2419024190
#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2419124191

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -12197,38 +12197,38 @@ typedef struct
1219712197
#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
1219812198
#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
1219912199

12200-
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po
12201-
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms
12200+
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
12201+
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
1220212202
#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
1220312203
#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
1220412204
#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
1220512205

12206-
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po
12207-
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms
12206+
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
12207+
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
1220812208
#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
1220912209
#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
1221012210
#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
1221112211

12212-
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po
12213-
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms
12212+
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
12213+
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
1221412214
#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
1221512215
#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
1221612216
#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
1221712217

12218-
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po
12219-
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms
12218+
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
12219+
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
1222012220
#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
1222112221
#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
1222212222
#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
1222312223

12224-
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po
12225-
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms
12224+
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
12225+
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
1222612226
#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
1222712227
#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
1222812228
#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
1222912229

12230-
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po
12231-
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms
12230+
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
12231+
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
1223212232
#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
1223312233
#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
1223412234
#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
@@ -16951,10 +16951,10 @@ typedef struct
1695116951
#define RNG_CR_CLKDIV_Pos (16U)
1695216952
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
1695316953
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
16954-
#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16955-
#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16956-
#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16957-
#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
16954+
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
16955+
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
16956+
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
16957+
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
1695816958
#define RNG_CR_RNG_CONFIG1_Pos (20U)
1695916959
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
1696016960
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
@@ -20392,7 +20392,7 @@ typedef struct
2039220392

2039320393
/******************* Bit definition for TIM_CCR5 register *******************/
2039420394
#define TIM_CCR5_CCR5_Pos (0U)
20395-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
20395+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
2039620396
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
2039720397
#define TIM_CCR5_GC5C1_Pos (29U)
2039820398
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
@@ -24197,7 +24197,7 @@ typedef struct
2419724197

2419824198
/******************************** HSEM Instances *******************************/
2419924199
#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
24200-
#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
24200+
#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */
2420124201
#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2420224202
#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
2420324203

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