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system(wb0) update STM32WB0x HAL Drivers to v1.5.0
Included in STM32CubeWB0 FW v1.5.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 37d9577 commit c1cbfd9

17 files changed

Lines changed: 203 additions & 117 deletions

‎system/Drivers/STM32WB0x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -363,7 +363,6 @@ extern "C" {
363363
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
364364
#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
365365
#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI
366-
#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI
367366
#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
368367

369368
#endif /* STM32L4 */
@@ -1918,7 +1917,11 @@ extern "C" {
19181917
#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
19191918
#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
19201919
#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
1921-
1920+
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
1921+
#define PWR_PVM_USB PWR_PVM_ENABLE
1922+
#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2
1923+
#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2
1924+
#endif /* STM32G0C1xx || STM32G0B1xx */
19221925
#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
19231926
#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
19241927
#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
@@ -2031,6 +2034,9 @@ extern "C" {
20312034

20322035
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
20332036
#endif
2037+
#if defined (STM32H7RS)
2038+
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO
2039+
#endif
20342040

20352041
/**
20362042
* @}
@@ -2159,6 +2165,13 @@ extern "C" {
21592165
#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig
21602166
#endif /* STM32H7RS || STM32N6 */
21612167

2168+
#if defined(STM32N6)
2169+
/* alias CMSIS */
2170+
#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos
2171+
#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk
2172+
#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN
2173+
#endif /* STM32N6 */
2174+
21622175
/**
21632176
* @}
21642177
*/

‎system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ extern "C" {
4848
* @brief HAL Driver version number
4949
*/
5050
#define __STM32WB0x_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
51-
#define __STM32WB0x_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
51+
#define __STM32WB0x_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
5252
#define __STM32WB0x_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
5353
#define __STM32WB0x_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
5454
#define __STM32WB0x_HAL_VERSION ((__STM32WB0x_HAL_VERSION_MAIN << 24U)\

‎system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_hal_uart.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1343,7 +1343,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)
13431343
* divided by the smallest oversampling used on the USART (i.e. 8)
13441344
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
13451345
*/
1346-
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001U)
1346+
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 2000000U)
13471347

13481348
/** @brief Check UART assertion time.
13491349
* @param __TIME__ 5-bit value assertion time.

‎system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h‎

Lines changed: 0 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -430,7 +430,6 @@ typedef struct
430430
*/
431431
__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
432432
{
433-
(void)DMAx;
434433
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
435434
}
436435

@@ -451,7 +450,6 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
451450
*/
452451
__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
453452
{
454-
(void)DMAx;
455453
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
456454
}
457455

@@ -472,7 +470,6 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
472470
*/
473471
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
474472
{
475-
(void)DMAx;
476473
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
477474
DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
478475
}
@@ -509,7 +506,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha
509506
*/
510507
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
511508
{
512-
(void)DMAx;
513509
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
514510
DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
515511
Configuration);
@@ -537,7 +533,6 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel,
537533
*/
538534
__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
539535
{
540-
(void)DMAx;
541536
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
542537
DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
543538
}
@@ -563,7 +558,6 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t
563558
*/
564559
__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
565560
{
566-
(void)DMAx;
567561
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
568562
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
569563
}
@@ -590,7 +584,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint
590584
*/
591585
__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
592586
{
593-
(void)DMAx;
594587
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC,
595588
Mode);
596589
}
@@ -614,7 +607,6 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_
614607
*/
615608
__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
616609
{
617-
(void)DMAx;
618610
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
619611
DMA_CCR_CIRC));
620612
}
@@ -639,7 +631,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
639631
*/
640632
__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
641633
{
642-
(void)DMAx;
643634
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC,
644635
PeriphOrM2MSrcIncMode);
645636
}
@@ -663,7 +654,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel
663654
*/
664655
__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
665656
{
666-
(void)DMAx;
667657
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
668658
DMA_CCR_PINC));
669659
}
@@ -688,7 +678,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha
688678
*/
689679
__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
690680
{
691-
(void)DMAx;
692681
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC,
693682
MemoryOrM2MDstIncMode);
694683
}
@@ -712,7 +701,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel
712701
*/
713702
__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
714703
{
715-
(void)DMAx;
716704
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
717705
DMA_CCR_MINC));
718706
}
@@ -738,7 +726,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha
738726
*/
739727
__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
740728
{
741-
(void)DMAx;
742729
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE,
743730
PeriphOrM2MSrcDataSize);
744731
}
@@ -763,7 +750,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u
763750
*/
764751
__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
765752
{
766-
(void)DMAx;
767753
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
768754
DMA_CCR_PSIZE));
769755
}
@@ -789,7 +775,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe
789775
*/
790776
__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
791777
{
792-
(void)DMAx;
793778
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE,
794779
MemoryOrM2MDstDataSize);
795780
}
@@ -814,7 +799,6 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u
814799
*/
815800
__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
816801
{
817-
(void)DMAx;
818802
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
819803
DMA_CCR_MSIZE));
820804
}
@@ -841,7 +825,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe
841825
*/
842826
__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
843827
{
844-
(void)DMAx;
845828
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL,
846829
Priority);
847830
}
@@ -867,7 +850,6 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t
867850
*/
868851
__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
869852
{
870-
(void)DMAx;
871853
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
872854
DMA_CCR_PL));
873855
}
@@ -892,7 +874,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3
892874
*/
893875
__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
894876
{
895-
(void)DMAx;
896877
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
897878
DMA_CNDTR_NDT, NbData);
898879
}
@@ -916,7 +897,6 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u
916897
*/
917898
__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
918899
{
919-
(void)DMAx;
920900
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
921901
DMA_CNDTR_NDT));
922902
}
@@ -948,7 +928,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe
948928
__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
949929
uint32_t DstAddress, uint32_t Direction)
950930
{
951-
(void)DMAx;
952931
/* Direction Memory to Periph */
953932
if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
954933
{
@@ -983,7 +962,6 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel,
983962
*/
984963
__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
985964
{
986-
(void)DMAx;
987965
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
988966
}
989967

@@ -1007,7 +985,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel
1007985
*/
1008986
__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1009987
{
1010-
(void)DMAx;
1011988
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress);
1012989
}
1013990

@@ -1029,7 +1006,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel
10291006
*/
10301007
__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
10311008
{
1032-
(void)DMAx;
10331009
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
10341010
}
10351011

@@ -1051,7 +1027,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha
10511027
*/
10521028
__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
10531029
{
1054-
(void)DMAx;
10551030
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
10561031
}
10571032

@@ -1075,7 +1050,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha
10751050
*/
10761051
__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
10771052
{
1078-
(void)DMAx;
10791053
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress);
10801054
}
10811055

@@ -1099,7 +1073,6 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel
10991073
*/
11001074
__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
11011075
{
1102-
(void)DMAx;
11031076
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
11041077
}
11051078

@@ -1121,7 +1094,6 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel
11211094
*/
11221095
__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
11231096
{
1124-
(void)DMAx;
11251097
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
11261098
}
11271099

@@ -1143,7 +1115,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha
11431115
*/
11441116
__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
11451117
{
1146-
(void)DMAx;
11471118
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
11481119
}
11491120

@@ -1166,7 +1137,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha
11661137
*/
11671138
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
11681139
{
1169-
(void)DMAx;
11701140
MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request);
11711141
}
11721142

@@ -1188,7 +1158,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel
11881158
*/
11891159
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
11901160
{
1191-
(void)DMAx;
11921161
return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID));
11931162
}
11941163

@@ -1928,7 +1897,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
19281897
*/
19291898
__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
19301899
{
1931-
(void)DMAx;
19321900
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
19331901
}
19341902

@@ -1949,7 +1917,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
19491917
*/
19501918
__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
19511919
{
1952-
(void)DMAx;
19531920
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
19541921
}
19551922

@@ -1970,7 +1937,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
19701937
*/
19711938
__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
19721939
{
1973-
(void)DMAx;
19741940
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
19751941
}
19761942

@@ -1991,7 +1957,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
19911957
*/
19921958
__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
19931959
{
1994-
(void)DMAx;
19951960
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
19961961
}
19971962

@@ -2012,7 +1977,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
20121977
*/
20131978
__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
20141979
{
2015-
(void)DMAx;
20161980
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
20171981
}
20181982

@@ -2033,7 +1997,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
20331997
*/
20341998
__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
20351999
{
2036-
(void)DMAx;
20372000
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
20382001
}
20392002

@@ -2054,7 +2017,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
20542017
*/
20552018
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
20562019
{
2057-
(void)DMAx;
20582020
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
20592021
DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
20602022
}
@@ -2076,7 +2038,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann
20762038
*/
20772039
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
20782040
{
2079-
(void)DMAx;
20802041
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
20812042
DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
20822043
}
@@ -2098,7 +2059,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann
20982059
*/
20992060
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
21002061
{
2101-
(void)DMAx;
21022062
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
21032063
DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
21042064
}

‎system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -445,8 +445,6 @@ __STATIC_INLINE uint32_t LL_RADIO_TIMER_IsEnabledCPUWakeupTimerForceSleeping(WAK
445445
__STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx, uint8_t mode)
446446
{
447447
#if defined(STM32WB09)
448-
(void)WAKEUPx; // No operation for STM32WB09
449-
(void)mode; // No operation for STM32WB09
450448
return;
451449
#else
452450
MODIFY_REG_FIELD(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE, (mode & 0x7));
@@ -462,7 +460,6 @@ __STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx,
462460
__STATIC_INLINE uint32_t LL_RADIO_TIMER_GetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx)
463461
{
464462
#if defined(STM32WB09)
465-
(void)WAKEUPx; // No operation for STM32WB09
466463
return 0;
467464
#else
468465
return (uint32_t)(READ_REG(WAKEUP->BLUE_SLEEP_REQUEST_MODE) & WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE);

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