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system(g0): update STM32G0xx CMSIS Drivers to v1.4.5
Included in STM32CubeG0 FW v1.6.3 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent cfba639 commit ccd2101

17 files changed

Lines changed: 270 additions & 77 deletions

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4037,6 +4037,12 @@ typedef struct
40374037
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
40384038
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
40394039

4040+
#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
4041+
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
4042+
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
4043+
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
4044+
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */
4045+
40404046
/*!< SWS configuration */
40414047
#define RCC_CFGR_SWS_Pos (3U)
40424048
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
@@ -4570,6 +4576,9 @@ typedef struct
45704576
*/
45714577
#define RTC_WAKEUP_SUPPORT
45724578
#define RTC_BACKUP_SUPPORT
4579+
#define RTC_TAMP_INT_NB 4u
4580+
#define RTC_TAMP_NB 2u
4581+
#define RTC_BACKUP_NB 5u
45734582

45744583
/******************** Bits definition for RTC_TR register *******************/
45754584
#define RTC_TR_PM_Pos (22U)
@@ -6309,7 +6318,7 @@ typedef struct
63096318

63106319
/******************* Bit definition for TIM_CCR5 register *******************/
63116320
#define TIM_CCR5_CCR5_Pos (0U)
6312-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
6321+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
63136322
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
63146323
#define TIM_CCR5_GC5C1_Pos (29U)
63156324
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3739,6 +3739,9 @@ typedef struct
37393739
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
37403740
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
37413741
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
3742+
#define PWR_CR2_PVMEN_DAC_Pos (7U)
3743+
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
3744+
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */
37423745

37433746
/******************** Bit definition for PWR_CR3 register ********************/
37443747
#define PWR_CR3_EWUP_Pos (0U)
@@ -3831,6 +3834,9 @@ typedef struct
38313834
#define PWR_SR2_PVDO_Pos (11U)
38323835
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
38333836
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
3837+
#define PWR_SR2_PVMO_DAC_Pos (15U)
3838+
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
3839+
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */
38343840

38353841
/******************** Bit definition for PWR_SCR register ********************/
38363842
#define PWR_SCR_CWUF_Pos (0U)
@@ -4217,6 +4223,12 @@ typedef struct
42174223
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
42184224
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
42194225

4226+
#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
4227+
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
4228+
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
4229+
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
4230+
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */
4231+
42204232
/*!< SWS configuration */
42214233
#define RCC_CFGR_SWS_Pos (3U)
42224234
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
@@ -4816,6 +4828,9 @@ typedef struct
48164828
*/
48174829
#define RTC_WAKEUP_SUPPORT
48184830
#define RTC_BACKUP_SUPPORT
4831+
#define RTC_TAMP_INT_NB 4u
4832+
#define RTC_TAMP_NB 2u
4833+
#define RTC_BACKUP_NB 5u
48194834

48204835
/******************** Bits definition for RTC_TR register *******************/
48214836
#define RTC_TR_PM_Pos (22U)
@@ -6573,7 +6588,7 @@ typedef struct
65736588

65746589
/******************* Bit definition for TIM_CCR5 register *******************/
65756590
#define TIM_CCR5_CCR5_Pos (0U)
6576-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
6591+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
65776592
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
65786593
#define TIM_CCR5_GC5C1_Pos (29U)
65796594
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3975,6 +3975,9 @@ typedef struct
39753975
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
39763976
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
39773977
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
3978+
#define PWR_CR2_PVMEN_DAC_Pos (7U)
3979+
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
3980+
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */
39783981

39793982
/******************** Bit definition for PWR_CR3 register ********************/
39803983
#define PWR_CR3_EWUP_Pos (0U)
@@ -4067,6 +4070,9 @@ typedef struct
40674070
#define PWR_SR2_PVDO_Pos (11U)
40684071
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
40694072
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
4073+
#define PWR_SR2_PVMO_DAC_Pos (15U)
4074+
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
4075+
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */
40704076

40714077
/******************** Bit definition for PWR_SCR register ********************/
40724078
#define PWR_SCR_CWUF_Pos (0U)
@@ -4453,6 +4459,12 @@ typedef struct
44534459
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
44544460
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
44554461

4462+
#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
4463+
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
4464+
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
4465+
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
4466+
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */
4467+
44564468
/*!< SWS configuration */
44574469
#define RCC_CFGR_SWS_Pos (3U)
44584470
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
@@ -5114,6 +5126,9 @@ typedef struct
51145126
*/
51155127
#define RTC_WAKEUP_SUPPORT
51165128
#define RTC_BACKUP_SUPPORT
5129+
#define RTC_TAMP_INT_NB 4u
5130+
#define RTC_TAMP_NB 2u
5131+
#define RTC_BACKUP_NB 5u
51175132

51185133
/******************** Bits definition for RTC_TR register *******************/
51195134
#define RTC_TR_PM_Pos (22U)
@@ -6877,7 +6892,7 @@ typedef struct
68776892

68786893
/******************* Bit definition for TIM_CCR5 register *******************/
68796894
#define TIM_CCR5_CCR5_Pos (0U)
6880-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
6895+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
68816896
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
68826897
#define TIM_CCR5_GC5C1_Pos (29U)
68836898
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4056,6 +4056,12 @@ typedef struct
40564056
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
40574057
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
40584058

4059+
#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
4060+
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
4061+
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
4062+
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
4063+
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */
4064+
40594065
/*!< SWS configuration */
40604066
#define RCC_CFGR_SWS_Pos (3U)
40614067
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
@@ -4616,6 +4622,9 @@ typedef struct
46164622
*/
46174623
#define RTC_WAKEUP_SUPPORT
46184624
#define RTC_BACKUP_SUPPORT
4625+
#define RTC_TAMP_INT_NB 4u
4626+
#define RTC_TAMP_NB 2u
4627+
#define RTC_BACKUP_NB 5u
46194628

46204629
/******************** Bits definition for RTC_TR register *******************/
46214630
#define RTC_TR_PM_Pos (22U)
@@ -6370,7 +6379,7 @@ typedef struct
63706379

63716380
/******************* Bit definition for TIM_CCR5 register *******************/
63726381
#define TIM_CCR5_CCR5_Pos (0U)
6373-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
6382+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
63746383
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
63756384
#define TIM_CCR5_GC5C1_Pos (29U)
63766385
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4075,6 +4075,9 @@ typedef struct
40754075
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
40764076
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
40774077
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
4078+
#define PWR_CR2_PVMEN_DAC_Pos (7U)
4079+
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
4080+
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */
40784081

40794082
/******************** Bit definition for PWR_CR3 register ********************/
40804083
#define PWR_CR3_EWUP_Pos (0U)
@@ -4167,6 +4170,9 @@ typedef struct
41674170
#define PWR_SR2_PVDO_Pos (11U)
41684171
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
41694172
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
4173+
#define PWR_SR2_PVMO_DAC_Pos (15U)
4174+
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
4175+
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */
41704176

41714177
/******************** Bit definition for PWR_SCR register ********************/
41724178
#define PWR_SCR_CWUF_Pos (0U)
@@ -4553,6 +4559,12 @@ typedef struct
45534559
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
45544560
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
45554561

4562+
#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
4563+
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
4564+
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
4565+
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
4566+
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */
4567+
45564568
/*!< SWS configuration */
45574569
#define RCC_CFGR_SWS_Pos (3U)
45584570
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
@@ -5191,6 +5203,9 @@ typedef struct
51915203
*/
51925204
#define RTC_WAKEUP_SUPPORT
51935205
#define RTC_BACKUP_SUPPORT
5206+
#define RTC_TAMP_INT_NB 4u
5207+
#define RTC_TAMP_NB 2u
5208+
#define RTC_BACKUP_NB 5u
51945209

51955210
/******************** Bits definition for RTC_TR register *******************/
51965211
#define RTC_TR_PM_Pos (22U)
@@ -6972,7 +6987,7 @@ typedef struct
69726987

69736988
/******************* Bit definition for TIM_CCR5 register *******************/
69746989
#define TIM_CCR5_CCR5_Pos (0U)
6975-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
6990+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
69766991
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
69776992
#define TIM_CCR5_GC5C1_Pos (29U)
69786993
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4311,6 +4311,9 @@ typedef struct
43114311
#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
43124312
#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
43134313
#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
4314+
#define PWR_CR2_PVMEN_DAC_Pos (7U)
4315+
#define PWR_CR2_PVMEN_DAC_Msk (0x1UL << PWR_CR2_PVMEN_DAC_Pos) /*!< 0x00000080 */
4316+
#define PWR_CR2_PVMEN_DAC PWR_CR2_PVMEN_DAC_Msk /*!< DAC supply voltage monitoring enable */
43144317

43154318
/******************** Bit definition for PWR_CR3 register ********************/
43164319
#define PWR_CR3_EWUP_Pos (0U)
@@ -4403,6 +4406,9 @@ typedef struct
44034406
#define PWR_SR2_PVDO_Pos (11U)
44044407
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
44054408
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
4409+
#define PWR_SR2_PVMO_DAC_Pos (15U)
4410+
#define PWR_SR2_PVMO_DAC_Msk (0x1UL << PWR_SR2_PVMO_DAC_Pos) /*!< 0x00008000 */
4411+
#define PWR_SR2_PVMO_DAC PWR_SR2_PVMO_DAC_Msk /*!< VDDA monitoring output flag */
44064412

44074413
/******************** Bit definition for PWR_SCR register ********************/
44084414
#define PWR_SCR_CWUF_Pos (0U)
@@ -4789,6 +4795,12 @@ typedef struct
47894795
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
47904796
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
47914797

4798+
#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
4799+
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
4800+
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
4801+
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
4802+
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */
4803+
47924804
/*!< SWS configuration */
47934805
#define RCC_CFGR_SWS_Pos (3U)
47944806
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
@@ -5489,6 +5501,9 @@ typedef struct
54895501
*/
54905502
#define RTC_WAKEUP_SUPPORT
54915503
#define RTC_BACKUP_SUPPORT
5504+
#define RTC_TAMP_INT_NB 4u
5505+
#define RTC_TAMP_NB 2u
5506+
#define RTC_BACKUP_NB 5u
54925507

54935508
/******************** Bits definition for RTC_TR register *******************/
54945509
#define RTC_TR_PM_Pos (22U)
@@ -7276,7 +7291,7 @@ typedef struct
72767291

72777292
/******************* Bit definition for TIM_CCR5 register *******************/
72787293
#define TIM_CCR5_CCR5_Pos (0U)
7279-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
7294+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
72807295
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
72817296
#define TIM_CCR5_GC5C1_Pos (29U)
72827297
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4185,6 +4185,12 @@ typedef struct
41854185
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
41864186
#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
41874187

4188+
#define RCC_CFGR_SW_HSISYS (0x00000000UL) /*!< HSISYS oscillator selection as system clock */
4189+
#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE oscillator selection as system clock */
4190+
#define RCC_CFGR_SW_PLLRCLK (0x00000002UL) /*!< PLLRCLK selection as system clock */
4191+
#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI oscillator selection as system clock */
4192+
#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE oscillator selection as system clock */
4193+
41884194
/*!< SWS configuration */
41894195
#define RCC_CFGR_SWS_Pos (3U)
41904196
#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
@@ -4768,6 +4774,9 @@ typedef struct
47684774
*/
47694775
#define RTC_WAKEUP_SUPPORT
47704776
#define RTC_BACKUP_SUPPORT
4777+
#define RTC_TAMP_INT_NB 4u
4778+
#define RTC_TAMP_NB 2u
4779+
#define RTC_BACKUP_NB 5u
47714780

47724781
/******************** Bits definition for RTC_TR register *******************/
47734782
#define RTC_TR_PM_Pos (22U)
@@ -6509,7 +6518,7 @@ typedef struct
65096518

65106519
/******************* Bit definition for TIM_CCR5 register *******************/
65116520
#define TIM_CCR5_CCR5_Pos (0U)
6512-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
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#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
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#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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#define TIM_CCR5_GC5C1_Pos (29U)
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#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

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