Skip to content

Commit facd247

Browse files
fpistmfpistm
committed
system(h5): update STM32H5xx CMSIS Drivers to v1.7.0
Included in STM32CubeH5 FW v1.7.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent a88ef64 commit facd247

29 files changed

Lines changed: 55389 additions & 543 deletions

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h543xx.h‎

Lines changed: 669 additions & 0 deletions
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h553xx.h‎

Lines changed: 672 additions & 0 deletions
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,10 @@
5656
#include "partition_stm32h563xx.h"
5757
#elif defined(STM32H562xx)
5858
#include "partition_stm32h562xx.h"
59+
#elif defined(STM32H553xx)
60+
#include "partition_stm32h553xx.h"
61+
#elif defined(STM32H543xx)
62+
#include "partition_stm32h543xx.h"
5963
#elif defined(STM32H533xx)
6064
#include "partition_stm32h533xx.h"
6165
#elif defined(STM32H523xx)

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h‎

Lines changed: 52 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -339,10 +339,11 @@ typedef struct
339339
*/
340340
typedef struct
341341
{
342-
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
343-
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
344-
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
345-
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
342+
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
343+
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
344+
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
345+
__IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */
346+
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
346347
} RNG_TypeDef;
347348

348349
/**
@@ -2690,6 +2691,7 @@ typedef struct
26902691
#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */
26912692
#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< COMP1 polarity selection bit */
26922693

2694+
26932695
#define COMP_CFGR1_ITEN_Pos (6U)
26942696
#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */
26952697
#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */
@@ -2706,6 +2708,7 @@ typedef struct
27062708
#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */
27072709
#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */
27082710

2711+
27092712
#define COMP_CFGR1_INMSEL_Pos (16U)
27102713
#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */
27112714
#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */
@@ -2965,42 +2968,42 @@ typedef struct
29652968
/******************************************************************************/
29662969
/******************** Bits definition for RNG_CR register *******************/
29672970
#define RNG_CR_RNGEN_Pos (2U)
2968-
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
2969-
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
2971+
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
2972+
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */
29702973
#define RNG_CR_IE_Pos (3U)
2971-
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
2972-
#define RNG_CR_IE RNG_CR_IE_Msk
2974+
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
2975+
#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */
29732976
#define RNG_CR_CED_Pos (5U)
2974-
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
2975-
#define RNG_CR_CED RNG_CR_CED_Msk
2977+
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
2978+
#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */
29762979
#define RNG_CR_ARDIS_Pos (7U)
2977-
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
2978-
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
2980+
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */
2981+
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */
29792982
#define RNG_CR_RNG_CONFIG3_Pos (8U)
2980-
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
2981-
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
2983+
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
2984+
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */
29822985
#define RNG_CR_NISTC_Pos (12U)
2983-
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
2984-
#define RNG_CR_NISTC RNG_CR_NISTC_Msk
2986+
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
2987+
#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */
29852988
#define RNG_CR_RNG_CONFIG2_Pos (13U)
2986-
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
2987-
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
2989+
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
2990+
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */
29882991
#define RNG_CR_CLKDIV_Pos (16U)
2989-
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
2990-
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
2991-
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
2992-
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
2993-
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
2994-
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
2992+
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
2993+
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */
2994+
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
2995+
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
2996+
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
2997+
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
29952998
#define RNG_CR_RNG_CONFIG1_Pos (20U)
2996-
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
2997-
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
2999+
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
3000+
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */
29983001
#define RNG_CR_CONDRST_Pos (30U)
2999-
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
3000-
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
3002+
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
3003+
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */
30013004
#define RNG_CR_CONFIGLOCK_Pos (31U)
3002-
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
3003-
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
3005+
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
3006+
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */
30043007

30053008
/******************** Bits definition for RNG_SR register *******************/
30063009
#define RNG_SR_DRDY_Pos (0U)
@@ -3019,6 +3022,25 @@ typedef struct
30193022
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
30203023
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
30213024

3025+
/******************** Bits definition for RNG_NSCR register *******************/
3026+
#define RNG_NSCR_EN_OSC1_Pos (0U)
3027+
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
3028+
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk
3029+
#define RNG_NSCR_EN_OSC2_Pos (3U)
3030+
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
3031+
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk
3032+
#define RNG_NSCR_EN_OSC3_Pos (6U)
3033+
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
3034+
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk
3035+
#define RNG_NSCR_EN_OSC4_Pos (9U)
3036+
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
3037+
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk
3038+
#define RNG_NSCR_EN_OSC5_Pos (12U)
3039+
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
3040+
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk
3041+
#define RNG_NSCR_EN_OSC6_Pos (15U)
3042+
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
3043+
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk
30223044

30233045
/******************** Bits definition for RNG_HTCR register *******************/
30243046
#define RNG_HTCR_HTCFG_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h‎

Lines changed: 51 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -368,10 +368,11 @@ typedef struct
368368
*/
369369
typedef struct
370370
{
371-
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
372-
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
373-
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
374-
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
371+
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
372+
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
373+
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
374+
__IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */
375+
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
375376
} RNG_TypeDef;
376377

377378
/**
@@ -4034,42 +4035,42 @@ typedef struct
40344035
/******************************************************************************/
40354036
/******************** Bits definition for RNG_CR register *******************/
40364037
#define RNG_CR_RNGEN_Pos (2U)
4037-
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
4038-
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
4038+
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
4039+
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */
40394040
#define RNG_CR_IE_Pos (3U)
4040-
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
4041-
#define RNG_CR_IE RNG_CR_IE_Msk
4041+
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
4042+
#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */
40424043
#define RNG_CR_CED_Pos (5U)
4043-
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
4044-
#define RNG_CR_CED RNG_CR_CED_Msk
4044+
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
4045+
#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */
40454046
#define RNG_CR_ARDIS_Pos (7U)
4046-
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
4047-
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
4047+
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */
4048+
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */
40484049
#define RNG_CR_RNG_CONFIG3_Pos (8U)
4049-
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
4050-
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
4050+
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
4051+
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */
40514052
#define RNG_CR_NISTC_Pos (12U)
4052-
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
4053-
#define RNG_CR_NISTC RNG_CR_NISTC_Msk
4053+
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
4054+
#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */
40544055
#define RNG_CR_RNG_CONFIG2_Pos (13U)
4055-
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
4056-
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
4056+
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
4057+
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */
40574058
#define RNG_CR_CLKDIV_Pos (16U)
4058-
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
4059-
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
4060-
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
4061-
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
4062-
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
4063-
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
4059+
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
4060+
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */
4061+
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
4062+
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
4063+
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
4064+
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
40644065
#define RNG_CR_RNG_CONFIG1_Pos (20U)
4065-
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
4066-
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
4066+
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
4067+
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */
40674068
#define RNG_CR_CONDRST_Pos (30U)
4068-
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
4069-
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
4069+
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
4070+
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */
40704071
#define RNG_CR_CONFIGLOCK_Pos (31U)
4071-
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
4072-
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
4072+
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
4073+
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */
40734074

40744075
/******************** Bits definition for RNG_SR register *******************/
40754076
#define RNG_SR_DRDY_Pos (0U)
@@ -4088,6 +4089,25 @@ typedef struct
40884089
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
40894090
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
40904091

4092+
/******************** Bits definition for RNG_NSCR register *******************/
4093+
#define RNG_NSCR_EN_OSC1_Pos (0U)
4094+
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
4095+
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk
4096+
#define RNG_NSCR_EN_OSC2_Pos (3U)
4097+
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
4098+
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk
4099+
#define RNG_NSCR_EN_OSC3_Pos (6U)
4100+
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
4101+
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk
4102+
#define RNG_NSCR_EN_OSC4_Pos (9U)
4103+
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
4104+
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk
4105+
#define RNG_NSCR_EN_OSC5_Pos (12U)
4106+
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
4107+
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk
4108+
#define RNG_NSCR_EN_OSC6_Pos (15U)
4109+
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
4110+
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk
40914111

40924112
/******************** Bits definition for RNG_HTCR register *******************/
40934113
#define RNG_HTCR_HTCFG_Pos (0U)
@@ -10828,7 +10848,7 @@ typedef struct
1082810848
/**************** Bit definition for XSPI_DCR3 register ******************/
1082910849
#define XSPI_DCR3_CSBOUND_Pos (16U)
1083010850
#define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
10831-
#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */
10851+
#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< NCS boundary */
1083210852

1083310853
/**************** Bit definition for XSPI_DCR4 register ******************/
1083410854
#define XSPI_DCR4_REFRESH_Pos (0U)

0 commit comments

Comments
 (0)