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perf(moe): fused clamped-SwiGLU activations for shared and routed experts (NVIDIA-NeMo#4286)
* perf(moe): compile the shared-expert clamped SwiGLU into one kernel
The shared-expert MLP of DeepSeek-V4 models runs its activation eagerly: two fp32
up-casts, two clamps, silu, a multiply and a down-cast — seven launches and two
fp32 temporaries per call, issued on the shared-expert side stream while the main
stream waits for them (the 16-node trace charges 9 ms/step of copies to this
forward). A fullgraph-compiled core over the separate gate / up projections gives
one fused kernel per direction with the same arithmetic; the eager chain stays for
CPU inputs. The test pins outputs bitwise and gradients, including the clamp masks.
Signed-off-by: Yisong Li <yisongbetter@gmail.com>
* perf(moe): Triton kernels for the clamped SwiGLU expert activation
The routed experts of DeepSeek-V4 models apply silu(clamp(gate)) * clamp(up) *
probs to the grouped-GEMM output through a fullgraph-compiled function whose
backward AOT autograd derives; that backward concatenates d_gate and d_up and
ran at about a quarter of HBM bandwidth on GB200 (0.7 ms per layer for a 1.1 GB
pass at the 16-node shape, 24 ms per step).
swiglu_triton adds one-pass kernels: a 2-D tiled forward and a backward that
walks the columns of a block of rows, writes d_gate / d_up into the two halves of
the input gradient and accumulates the per-row probability gradient in
registers. fp32 math, clamp gradients as torch.clamp (inclusive masks), results
rounded to the input dtype. swiglu_clamped_deepep dispatches to the kernels for
contiguous CUDA inputs when Triton imports and otherwise keeps the compiled
function. Tests compare against the eager fp32 reference on the GPU and pin the
dispatcher and the layout guard.
Signed-off-by: Yisong Li <yisongbetter@gmail.com>
* fix(moe): fp32 clamped-SwiGLU kernels under inductor; dynamic shared island
Under torch.compile inductor hands the user Triton kernels the Python-float `limit` as fp64, so the
math ran in fp64 and the backward kernel's loop-carried fp32 accumulator changed type ("Loop-carried
variable acc has initial type fp32 but is re-assigned to fp64"): fullgraph compilation of a module
around SwigluClampedTriton failed. Both kernels now cast `limit` to fp32 on entry and the row
accumulation is cast explicitly.
`_clamped_swiglu_act` was `@torch.compile(fullgraph=True, dynamic=False)`: with fullgraph, the
recompile limit is a hard failure (FailOnRecompileLimitHit) after `recompile_limit` distinct token
counts, which variable-length batches reach. The island now uses Dynamo's default shape policy (one
static graph, then one symbolic graph every later shape reuses).
Tests: autocast with FP32 parameters (BF16 and FP32 inputs) against the eager reference through a
projection, compiled module on CUDA (explain: one graph, no breaks; fullgraph forward + backward
through inductor), the dispatcher captured without breaks on CPU, and recompile_limit + 3 distinct
row counts through the island without a failure.
Signed-off-by: Yisong Li <yisongbetter@gmail.com>
* test(moe): keep the new SwiGLU contract tests under CI's 30 s runtime budget
CI's conftest refuses a changed test that requests a runtime_budget above 30 s (the recompile sweep
asked for 240 s, the compiled-module and dispatcher tests for 120 / 60 s), which failed every unit
shard of the previous head. The recompile test now re-wraps the island's own function with the eager
backend and a patched recompile limit, so it checks Dynamo's shape policy without inductor's CPU
build (the one-GPU contract probe sweeps the production island itself); the two compile tests keep
their inductor / Dynamo work and run well inside 30 s.
Signed-off-by: Yisong Li <yisongbetter@gmail.com>
---------
Signed-off-by: Yisong Li <yisongbetter@gmail.com>1 parent 4eb27cf commit fca8910
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