analog-ic-design

Common-Centroid Placement Algorithm for IC design elements

Generate folded-cascode opamp parameters with interactive CLI.

Deadlines for Conferences which are relevant to the research topics of E&D

Design and simulation of a two-stage CMOS OpAmp in Cadence Virtuoso. Verified via PVT corners and Monte Carlo analysis.

Reference voltage: 315 mV Supply range: 1.0 V -3.3 V Temperature coefficient: ≈ 15 ppm/°C (−40 °C to 125 °C)

# Low Noise Low Power Two-Stage CMOS Operational Amplifier. A transistor-level CMOS operational amplifier designed in Cadence Virtuoso using the GPDK180 technology. The design targets audio signal processing applications requiring low noise, high gain and low power consumption.

Design, simulation and full verification of a CMOS transimpedance amplifier.

This repository contains all the designs done by Shreyas Singh in the VLSI related Labs-Digital VLSI design(5th semester) and Current Mode Analog VLSI desig(6th sem)

Comparative study and design analysis of current mirror topologies in analog IC design.

Design, simulation(LTspice), and automated Python characterization of a Two-Stage Miller-Compensated CMOS Op-Amp in TSMC 0.18µm. Achieved 71 dB Gain, 52.1 MHz GBW, 63.3° Phase Margin, and 53.7 V/µs Slew Rate with deep-submicron short-channel tuning.

A 2.7μW, 127dB CMRR 3-OpAmp Instrumentation Amplifier with Driven-Right-Leg feedback for wearable biopotential monitoring in 180nm CMOS.

Documentation and performance reports for an ultra-low-power dual-loop LDO of PMIC designed during my internship.

Transistor-level design of a low-power (1.18mW) Two-Stage Folded-Cascode OTA in 0.18µm CMOS. Optimized for high DC gain and bandwidth utilizing the systematic gm/ID sizing methodology.

CMOS PWM Generator designed and simulated in LTspice. The project demonstrates pulse-width modulation using a behavioral ramp source, transistor-level CMOS comparator, and CMOS output logic operating from a 1.8 V supply. It serves as an early-stage mixed-signal IC design prototype.

MY JOURNEY TO BE AN ANALOG IC ENGINEER . Self-learning projects using industry standard EDA tools. [Work-In-Progress]

Engineering traceability framework for Cadence Virtuoso ADE XL using SKILL and Python.

Research portfolio on analog layout techniques, structure-aware generation, B*-tree placement, well-domain repair, and access-aware routing.

Analog IC design portfolio: two OTA mini projects, bandgap and Monticelli class-AB design challenges, 17 technical reports, and an interactive results website.

Transistor-level LTspice study of a standard 6T SRAM cell, Single Event Upset fault injection, and a radiation-hardened DICE memory cell for space electronics applications.

Open-source subthreshold VGA core for hearing-aid audio compression — SKY130, gm/ID-driven flow. IEEE SSCS Code-a-Chip ISSCC'27 submission