axi4-protocol

Here are 11 public repositories matching this topic...

dpretet / axi-crossbar

Parametric AXI4 crossbar in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated May 25, 2026
SystemVerilog

dpretet / friscv

Sponsor

Star

RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Aug 28, 2026
SystemVerilog

arhamhashmi01 / Axi4-lite

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This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface

Updated May 4, 2024
SystemVerilog

therealczr15 / NYCU_ICLAB_2024S

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Spring 2024 NYCU Integrated Circuit Design Laboratory (ICLAB)

pipeline rtl verilog finite-state-machine sram systemverilog dram cell-based apr combinational-circuit sequential-circuits axi4-protocol jaspergold cross-clock-domain digital-ic-design

Updated Mar 5, 2025
Verilog

yunusesergun / yesergun.fpga.dev

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All about FPGA...

fpga clock vhdl rtl verilog vivado axi4-protocol

Updated Feb 28, 2026
Tcl

muhammadtalhasami / Axi4_lite_interface

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This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog

Updated May 4, 2024
SystemVerilog

CSpyridakis / Reconfigurable-Computing

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Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

fpga zynq hls vhdl xilinx vivado vivado-hls zynq-7000 evaluation-board rsoc axi4 axi4-lite reconfigurable-computing axi4-protocol axi4-stream-protocol

Updated Oct 13, 2020
C++

kirthana1181 / AXI4-Lite-based_Data-Sorter

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In this repository, an AXI4-Lite Protocol Slave Peripheral Transaction has been coded that can receive data packets, validate them based on sorting condition valid or invalid storage. The design of storages is a simple FIFO-like sorting.

verilog-hdl verilog-project axi4-lite axi4-protocol rtl-design

Updated Jan 15, 2026
JavaScript

sbaldzenka / axi_gpio

Star

GPIO IP-core with AXI4-Lite bus interface.

gpio fpga rtl systemverilog modelsim fpga-soc testbench axi4-lite axi4-protocol axi4-lite-interface

Updated Aug 21, 2026
SystemVerilog

Raveem13 / axi4-mem-vip

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SystemVerilog UVM verification IP for an AXI4 memory slave supporting INCR bursts, outstanding transactions, ID-based ordering, write strobes, and protocol SVA assertions.

verification-methodologies axi4-protocol axi4-full uvm-verification

Updated Apr 19, 2026
SystemVerilog

denisastanut / Axi4-Stream-Sensor-Processing

Star

An FPGA-based temperature processing system on Basys 3 using AXI4-Stream architecture. It captures sensor data via UART, applies a sliding average filter, and tracks real-time Min/Max values.

fpga vhdl basys3 sliding-window axi4-protocol

Updated Jan 19, 2026
VHDL

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