32-bit Superscalar RISC-V CPU
CPU Benchmarks Set
LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.
A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)
Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.
Forth language port of CoreMark benchmark (https://www.eembc.org/coremark)
5-stage RV32IM RISC-V CPU and FPGA SoC in SystemVerilog, featuring forwarding, hazard control, machine-mode CSR/traps, precise timer interrupts, TCM, UART, GPIO, and FreeRTOS bring-up.
ArduinoCoreMark is a CPU performance benchmark for Arduino platform based on EEMBC CoreMark.
Architecture and Performance Evaluation of EEMBC::CoreMark benchmark on BOOM CPUs (Small & Large).
This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC
Cycle-approximate out-of-order RISC-V CPU simulator with TAGE branch prediction, store-to-load forwarding, and a genetic algorithm for design space exploration using real CoreMark execution.
A stable version of nexus-am (created by jyy).
Performance evaluation of Stage0 (PCGen & Branch Predictor) variants in SHAKTI C-Class RISC-V core RTL — CEG Fabless Internship 2025
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