d-flipflop

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digital-logic-design d-flipflop micro-processor flip-flops k-map proteus-v8 4-bit-comparator jk-flipflop 5-bit-comparator 8-bit-comparator sr-flip-flop

Updated Aug 2, 2023

roman-komac / NPMP_BIO

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NPMP 2017/18 - BIO seminar D master-slave flip-flop

counter biological-simulations d-flipflop bsim synchronous-flipflop

Updated Jan 18, 2018
Java

levyashvin / verilog_codes

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basic implementation of logic structures using verilog (revising github)

registers pipo d-flipflop full-adder sipo sequence-detector siso piso verilog-testbenches synchronous-counter priority-encoder jk-flipflop t-flipflop sr-flip-flop full-subtractor half-subtractor

Updated Feb 29, 2024
Verilog

SURIYA-R-K / fsm-sequence-detector

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Detects the binary sequence 1010 using a high-speed Mealy FSM with TSPC D Flip-Flops in Cadence Virtuoso. Supports overlapping detection and transient verification (90 nm GPDK).

fsm simulation waveform schematic spectre vlsi state-diagram cadence-virtuoso cadence digital-design mealy-machine virtuoso d-flipflop sequence-detector tspc

Updated Jan 10, 2026

newajsharif91 / Verilog_HDL_Digital-System-Design

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CSE-2112 Digital Syatem Design LAb

verilog adder flip-flop half-adder d-flipflop full-adder

Updated Jan 20, 2023
Verilog

Ujjwal1810 / Verification_enviornment

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Verification environments of communication and bus protocol

fifo uart-protocol i2c-protocol spi-protocol d-flipflop

Updated Dec 17, 2023

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