This repository provides the source code for RISE framework. RISE can be used as a generic framework Real-Time Intelligent Video Surveillance on FPGA.
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Oct 10, 2017 - C++
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hw-sw-codesign
Here are 9 public repositories matching this topic...
🎥 Explore how video generators can reveal implicit world rules with RISE-Video, enhancing understanding in computer vision research.
music player ui-design xaml csharp customization uwp media media-player help-wanted omp fluent-design real-time-video-analysis hw-sw-codesign winui media-players help-welcome
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Sep 15, 2026 - Python
INT8 Systolic-Array AI Accelerator on Zynq SoC with HW-SW Co-Design and Roofline Performance Analysis
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Mar 20, 2026 - Jupyter Notebook
Image super-resolution carved into silicon (FPGA Ignite 2024)
accelerator image-processing riscv hardware-acceleration risc-v image-super-resolution hw-sw-codesign hw-sw-co-design image-upscaling
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Jun 7, 2025 - VHDL
HW/SW co-simulation of a radar collision monitor on Zynq-7000. MATLAB stimulus → VHDL RTL → AXI4-Lite SoC → SystemVerilog testbench with Zynq VIP. Fully simulation-verified.
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Apr 25, 2026 - Verilog
Integração de HPS para FPGA por meio de Biblioteca Assembly na Cyclone V
c fpga assembly computer-engineering verilog de1-soc pbl quartus hw-sw-codesign matrix-operations hps
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Jun 6, 2025 - HTML
Hardware-software co-design for BitNet inference on multicore RISC-V using CVA6, Ara (RVV), and a ternary-optimized Gemmini.
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Apr 8, 2026
Hardware/software co-design of pipelined AES-128 using Zynq SoC for IIoT gateways
cryptography fpga zynq aes-128 verilog iiot hw-sw-codesign axi4-lite hardware-accelerator kria-kv260
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Jun 20, 2026 - Verilog
HW-SW Co-Design framework for custom NPU: Parameterized systolic array RTL verification via cocotb and multi-objective design space exploration (DSE) with analytical performance modeling.
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Jun 11, 2026 - Python
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