Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.
fpga matlab verilog digital-signal-processing verilog-hdl low-pass-filter direct-digital-synthesizer verilog-project fpga-programming phase-accumulator sine-wave-generator
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Updated
May 26, 2024 - Verilog