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riscv32im

Here are 14 public repositories matching this topic...

risc0 / risc0-lean4

A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover

riscv lean risc-v zero-knowledge riscv32 riscv32im lean4 zkvm risc0 zk-stark

Updated Feb 14, 2023
Lean

djzenma / RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

Updated May 29, 2020
Verilog

merledu / buraq_mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

chisel3 risc-v riscv32im open-mpw buraq-mini

Updated Jan 19, 2022
Scala

jesseopdenbrouw / thuas-riscv

The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zimop Zba Zbb Zbs Zbkb Sdext Sdtrig System-on-a-Chip in VHDL

fpga hardware vhdl riscv soc riscv32 rv32im riscv32im

Updated Aug 26, 2026
C

pixelspark / rv32jit

A RISC-V (rv32imc) assembler for JITing on the ESP32

rust esp32 risc-v riscv32 riscv32im esp32-c3

Updated Nov 1, 2023
Rust

xiaomi0530 / SXQ-RV32ICPU

cpu fpga riscv soc fpga-soc riscv32 riscv32im

Updated May 5, 2026
C

af-afk / ocaml-riscv32im-stylus

Ethereum RISCV32IM simulator that decodes and runs ELF, with ecalls for Stylus-friendly Ethereum operations.

ocaml stylus riscv web3 risc riscv32 riscv32im arbitrum risc-zero

Updated Aug 1, 2025
OCaml

Okdusty / esp32p4-rv32ima

Run Linux on ESP32-P4 (32MB psram) with this RISC-V emulator

esp32 linux-kernel riscv riscv32 riscv-linux riscv-emulator riscv32im linux-custom-image esp32p4

Updated Aug 31, 2026
C

Duy-Thanh / riscv

A cross-platform RISC-V emulator written in Object Pascal

riscv riscv32 riscv-linux riscv-emulator riscv32im riscv32i

Updated Jul 27, 2026
Pascal

lbnlmosaic / picorv32-toolchain

Container to build the RISC-V toolchains for PicoRV32

mosaic picorv32 riscv32 riscv32im riscv32i riscv32imc riscv32ic

Updated Jul 30, 2026
Dockerfile

Deadly-pro / Omni-RISC

RISC-V Accelerated Processing Unit — RV32IM 5-stage CPU + SIMT GPU on FPGA (Xilinx Artix-7). Verilator-verified (riscv-arch-test 53/54), MSI-coherent dual-core research rig, Vivado synthesis flow.

fpga gpu riscv verilog vivado soc apu riscv32im

Updated Aug 26, 2026
C++

hnkhushi / RISC-V-RV32IM-Processor-Verilog

RV32IM Processor based on RISC-V ISA written in Verilog. A hybrid processor which uses single cycle for the main RV32I data path and multi-cycle for the M extension including MUL/DIV operations.

verilog risc-v riscv32im processordesign

Updated May 7, 2026
Verilog

amamory-ursa / riscv-gnu-toolchain-docker

Dockerfile for RISC-V GNU Compiler Toolchain

riscv32 qemu-riscv riscv32im

Updated Dec 17, 2019
Dockerfile

RISCuinho / emulsiV

A visual simulator, criado por @guillaum Savaton, for teaching computer architecture using the RISC-V instruction set

riscv risc-v riscv-simulator riscv32im

Updated Jun 25, 2021
JavaScript

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