SPIFFS Bitstreamloader for the Spartan Edge Accelerator Board
High-performance discrete-time voltage-mode PID controller for a 100 kHz synchronous buck converter implemented on a Xilinx Spartan-7 FPGA. Features parallel hardware execution, 23-bit fixed-point precision, dual-stage saturation, and cycle-accurate verification. Validated on physical hardware.
This project implements a Finite State Machine (FSM) driven vending machine on a Xilinx Spartan-7 (XC7S50-CSGA324-1) FPGA.
FPGA Tetris implemented in SystemVerilog with HDMI output and Bluetooth controls through an ESP32-WROOM-32.
8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA
A Verilog-based implementation of a 4-bit Binary Coded Hexadecimal to 7-Segment Display Decoder on Spartan-7 FPGA. The design converts binary inputs into human-readable hexadecimal digits (0–F) and displays them in real-time. It includes modular RTL design, simulation, synthesis, and hardware verification using Xilinx Vivado.
This project mainly focuses on building an ALU which performs arithmetic and logic functions using verilog and FPGA
Real-time HDMI Pong game implemented in Verilog on a Spartan-7 FPGA
FPGA UART transmitter/receiver subsystem with 16× oversampling, parity/framing checks, internal loopback, and seven-segment display support in Verilog.
Custom application-specific processor for neural-network inference: MIPS-like ISA, Verilog datapath, assembler written from scratch, 50 MHz on Spartan-7.
A 32-bit RISC-V (RV32I + mul) soft processor written from scratch in SystemVerilog, running on a Spartan-7 FPGA at 100 MHz. Multicycle FSM, dual-port BRAM, blocking byte I/O over a custom FIFO - verified byte-exact against a golden ISA simulator across 10 compiled-C programs, in simulation and on hardware.
To associate your repository with the spartan-7 topic, visit your repo's landing page and select "manage topics."