Implementation of "Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks." 2021 58th ACM/IEEE Design Automation Conference (DAC).
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Updated
Feb 8, 2023 - Python
Implementation of "Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks." 2021 58th ACM/IEEE Design Automation Conference (DAC).
Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).
Generation of test pattern or input vector for a given circuit consisting of stuck-at faults and to also determine the expected output. Submitted as part of the Grand Finale of Google Girl Hackathon 2023.
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
VLSI test project: 4-bit ripple carry adder with random stuck-at fault injection. Supports ATPG-based verification, fault modeling, and simulation for learning and experimentation
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