tang-primer-20k

Beginner-friendly open-source FPGA IDE for Sipeed Tang Nano and Tang Primer: Verilog/SystemVerilog, simulation, waveforms, synthesis, JTAG, flash, and UART.

HDMI monitor on a Tang Primer 20K with the open-source Gowin toolchain — FPGA-served EDID, open TMDS receiver, genlocked scaler, zero hardware mods

One-file Windows installer for Tang FPGA Studio: beginner-friendly Verilog/SystemVerilog IDE and open-source Tang Nano/Primer toolchain.

Housing for Sipeed Tang Primer 20K

An MP3 player built entirely in FPGA gates — no CPU, no firmware. Pure-RTL MPEG-1 Layer III decoder on a Tang Primer 20K, fully open Gowin toolchain.

Self-contained RISC-V Linux machine on a Sipeed Tang Primer 20K FPGA — a VexRiscv-SMP soft CPU (LiteX) running mainline 32-bit Linux, with an LCD framebuffer console and a USB keyboard driven through the dock's USB3317 PHY in 6-pin ULPI serial mode.

This repository is used for the Inteligent Chip Design course on RTL development for a physical HDMI peripheral

Develop FPGA designs for the Sipeed Tang Primer 20K with a complete IDE featuring simulation, waveform inspection, build tools, and JTAG support.