uart-receiver

Must-have verilog systemverilog modules

Serial communication (USART) on the ATMega 2560 using C++ classes

UART receive task

Low resource UART receiver for FPGA.

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

Universal Asynchronous Receiver Transmitter

Contents presented in the Microcontrollers Laboratory Course; Microcontrollers used: Arduino UNO R3 & DOIT ESP32 DEVKIT V1 - CSE Department, Shiraz University, Spring 2025

This is an ESP32 project for receiving json from another device by uart and send it to the server. Also provide web service for management.

UART (Universal Asynchronous Receiver-Transmitter) is a widely used,, cost-effective serial communication protocol that facilitates data exchange between microcontrollers and peripheral devices using only two wires—Transmit (TX) and Receive (RX). It operates asynchronously, meaning it relies on matched baud rates rather than a shared clock signal

SystemVerilog UART transciever

Phase-2 Cycle-1: RTL Protocol Foundations

An Android app built with Kotlin and Jetpack Compose to talk to microcontrollers and serial hardware over a standard USB OTG cable.

Verilog HDL implementation, simulation, and functional verification of a UART Transmitter and Receiver using Intel Quartus Prime and ModelSim.

Serial dashboards and control-loop sandboxes, no GUI code. Showcase repo — source available on request.

Device connection and data transmission via UART - simple example

If we run out of input pins on FPGA, we can instantiate receiver of uart in DUT (design under test). Receiver will receive data from PC serially and convert this serial data to parallel data and give it to DUT to use it without hesitation of shortage of input pins.

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Complete RTL-to-GDSII implementation of a UART IP Core using Verilog HDL and the OpenLane2 ASIC design flow with the SkyWater SKY130 PDK. Includes RTL design, functional verification, synthesis, physical design, timing analysis, DRC/LVS verification, and final GDSII layout.