vhdl

Digital logic design tool and simulator

A FPGA friendly 32 bit RISC-V CPU implementation

VHDL 2008/93/87 simulator

cocotb: Python-based chip (RTL) verification

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Scala based HDL

Haskell to VHDL/Verilog/SystemVerilog compiler

Package manager and build abstraction tool for FPGA/ASIC development

Modular hardware build system

Hardware Description Languages

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

VHDL compiler and simulator

VUnit is a unit testing framework for VHDL/SystemVerilog

An abstraction library for interfacing EDA tools

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A tiny Open POWER ISA softcore written in VHDL 2008

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

A List of Free and Open Source Hardware Verification Tools and Frameworks

The PoC Library has been forked to github.com/VHDL/PoC. See new address below