Support GD32F30X DMA IRQ in USART config

Add a GD32F30X-specific NVIC branch in UsartDmaConfig to set priority and enable DMA1_Channel3_Channel4_IRQn. Previously non-F4 targets always used DMA1_Channel4_IRQn; this change configures the correct IRQ name for the GD32F30X series so DMA interrupts are set up properly.

Author: vanvught

lib-dmx/src/gd32/dmx.cpp

@@ -2450,7 +2450,10 @@ static void UsartDmaConfig() {
     dma_channel_subperipheral_select(UART3_DMAx, UART3_TX_DMA_CHx, UART3_TX_DMA_SUBPERIx);
 #endif
     Gd32DmaInterruptDisable<UART3_DMAx, UART3_TX_DMA_CHx, DMA_INTERRUPT_DISABLE>();
-#if !defined(GD32F4XX)
+#if defined(GD32F30X)
+    NVIC_SetPriority(DMA1_Channel3_Channel4_IRQn, 1);
+    NVIC_EnableIRQ(DMA1_Channel3_Channel4_IRQn);
+#elif !defined(GD32F4XX)
     NVIC_SetPriority(DMA1_Channel4_IRQn, 1);
     NVIC_EnableIRQ(DMA1_Channel4_IRQn);
 #else