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vanvughtvanvught
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Refactor GD32 lib: API renames & softuart rewrite
Cleanup and refactor of lib-gd32 sources and headers: - Removed an accidental/duplicate FMC source file. - Added IWYU keep comments to gd32 includes and bumped copyright years to 2026. - Introduced and aligned DMA macros (interrupt macros, naming) and cleaned up Gd32Dma* helpers for consistent formatting and behavior across GD32 families. - Enclosed ENET helpers in gd32::enet, renamed several Gd32Enet* helpers to clearer names (e.g. DescInformationGet, ClearDmaTxFlagsAndResume, HandleRxBufferUnavailable, ResetHash, FilterFeatureDisable/Enable, FilterSetHash) and normalized braces/formatting. - Updated UART headers and implementation: formatting, small API/name cleanups, IWYU comments, and consistent inline/template formatting. - Minor fixes/refactors in PWM and SPI/I2S DMA sources (formatting, constants, naming). - Renamed gd32_mac_address.cpp to macaddress.cpp and adjusted function name and copyright. - Major rewrite of softuart0/uart0.cpp: normalized macros, made timer/baud constants constexpr, replaced old circular buffer/state logic with clearer Tx/Rx state machines, implemented IRQ handler and safe buffer enqueue (PutCharTimer), added conditional RX support and static asserts, and improved concurrency handling around IRQs. Overall these changes improve consistency, naming, portability across GD32 variants, and reorganize the soft UART logic for reliability and readability.
1 parent ebb3f25 commit 67b9d13

14 files changed

Lines changed: 551 additions & 564 deletions

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‎lib-gd32/gd32f10x/GD32F10x_standard_peripheral/Source/.!60814!gd32f10x_fmc.c‎

Lines changed: 0 additions & 41 deletions
This file was deleted.

‎lib-gd32/include/gd32_dma.h‎

Lines changed: 40 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -29,27 +29,34 @@
2929
#include <cstdint>
3030
#include <cassert>
3131

32-
#include "gd32.h"
32+
#include "gd32.h" // IWYU pragma: keep
3333

3434
#if defined(GD32F4XX) || defined(GD32H7XX)
35-
#define DMA_PARAMETER_STRUCT dma_single_data_parameter_struct
36-
#define DMA_CHMADDR DMA_CHM0ADDR
37-
#define DMA_MEMORY_TO_PERIPHERAL DMA_MEMORY_TO_PERIPH
38-
#define DMA_PERIPHERAL_WIDTH_8BIT DMA_PERIPH_WIDTH_8BIT
39-
#define dma_init dma_single_data_mode_init
40-
#define dma_struct_para_init dma_single_data_para_struct_init
35+
#define DMA_PARAMETER_STRUCT dma_single_data_parameter_struct
36+
#define DMA_CHMADDR DMA_CHM0ADDR
37+
#define DMA_MEMORY_TO_PERIPHERAL DMA_MEMORY_TO_PERIPH
38+
#define DMA_PERIPHERAL_TO_MEMORY DMA_PERIPH_TO_MEMORY
39+
#define DMA_PERIPHERAL_WIDTH_8BIT DMA_PERIPH_WIDTH_8BIT
40+
#define dma_init dma_single_data_mode_init
41+
#define dma_struct_para_init dma_single_data_para_struct_init
4142
#define dma_memory_to_memory_disable(x, y)
43+
#define DMA_INTERRUPT_ENABLE (DMA_CHXCTL_FTFIE)
44+
#define DMA_INTERRUPT_DISABLE (DMA_CHXCTL_FTFIE | DMA_CHXCTL_HTFIE | DMA_CHXFCTL_FEEIE)
45+
#define DMA_INTERRUPT_FLAG_GET (DMA_INT_FLAG_FTF)
46+
#define DMA_INTERRUPT_FLAG_CLEAR (DMA_INT_FLAG_FTF | DMA_INT_FLAG_TAE)
4247
#else
43-
#define DMA_PARAMETER_STRUCT dma_parameter_struct
48+
#define DMA_PARAMETER_STRUCT dma_parameter_struct
49+
#define DMA_INTERRUPT_ENABLE (DMA_INT_FTF)
50+
#define DMA_INTERRUPT_DISABLE (DMA_INT_FTF | DMA_INT_HTF | DMA_INT_ERR)
51+
#define DMA_INTERRUPT_FLAG_GET (DMA_INT_FLAG_FTF)
52+
#define DMA_INTERRUPT_FLAG_CLEAR (DMA_INT_FLAG_FTF | DMA_INT_FLAG_G)
4453
#endif
4554

4655
#if defined(GD32F10X) || defined(GD32F30X)
47-
template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline bool Gd32DmaInterruptFlagGet()
48-
{
56+
template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline bool Gd32DmaInterruptFlagGet() {
4957
uint32_t interrupt_enable = 0, interrupt_flag = 0;
5058

51-
switch (flag)
52-
{
59+
switch (flag) {
5360
case DMA_INT_FLAG_FTF:
5461
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
5562
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
@@ -69,13 +76,11 @@ template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline
6976
return interrupt_flag && interrupt_enable;
7077
}
7178
#elif defined(GD32F20X)
72-
template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline bool Gd32DmaInterruptFlagGet()
73-
{
79+
template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline bool Gd32DmaInterruptFlagGet() {
7480
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
7581
uint32_t gif_check = 0x0FU, gif_enable = 0x0EU;
7682

77-
switch (flag)
78-
{
83+
switch (flag) {
7984
case DMA_INT_FLAG_FTF:
8085
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
8186
interrupt_flag = interrupt_flag >> ((channelx) * 4U);
@@ -103,14 +108,11 @@ template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline
103108
return (interrupt_flag && interrupt_enable);
104109
}
105110
#elif defined(GD32F4XX) || defined(GD32H7XX)
106-
template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline bool Gd32DmaInterruptFlagGet()
107-
{
111+
template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline bool Gd32DmaInterruptFlagGet() {
108112
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
109113

110-
if constexpr (channelx < DMA_CH4)
111-
{
112-
switch (flag)
113-
{
114+
if constexpr (channelx < DMA_CH4) {
115+
switch (flag) {
114116
case DMA_INTF_FEEIF:
115117
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx);
116118
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@@ -135,12 +137,9 @@ template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline
135137
[[unlikely]] assert(false && "Invalid flag");
136138
break;
137139
}
138-
}
139-
else if constexpr (channelx <= DMA_CH7)
140-
{
140+
} else if constexpr (channelx <= DMA_CH7) {
141141
constexpr uint32_t kChannelFlagOffset = static_cast<uint32_t>(channelx) - 4;
142-
switch (flag)
143-
{
142+
switch (flag) {
144143
case DMA_INTF_FEEIF:
145144
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, kChannelFlagOffset);
146145
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@@ -165,9 +164,7 @@ template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline
165164
[[unlikely]] assert(false && "Invalid flag");
166165
break;
167166
}
168-
}
169-
else
170-
{
167+
} else {
171168
[[unlikely]] assert(false && "Invalid channelx");
172169
}
173170

@@ -178,19 +175,14 @@ template <uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag> inline
178175
#endif
179176

180177
#if defined(GD32F10X) || defined(GD32F30X) || defined(GD32F20X)
181-
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nFlag> void Gd32DmaInterruptFlagClear()
182-
{
178+
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nFlag> void Gd32DmaInterruptFlagClear() {
183179
DMA_INTC(peripheral) |= DMA_FLAG_ADD(nFlag, channel);
184180
}
185181
#elif defined(GD32F4XX) || defined(GD32H7XX)
186-
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nFlag> inline void Gd32DmaInterruptFlagClear()
187-
{
188-
if constexpr (channel < DMA_CH4)
189-
{
182+
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nFlag> inline void Gd32DmaInterruptFlagClear() {
183+
if constexpr (channel < DMA_CH4) {
190184
DMA_INTC0(peripheral) |= DMA_FLAG_ADD(nFlag, channel);
191-
}
192-
else
193-
{
185+
} else {
194186
DMA_INTC1(peripheral) |= DMA_FLAG_ADD(nFlag, static_cast<uint32_t>(channel) - 4U);
195187
}
196188
}
@@ -199,41 +191,30 @@ template <uint32_t peripheral, dma_channel_enum channel, uint32_t nFlag> inline
199191
#endif
200192

201193
#if defined(GD32F10X) || defined(GD32F30X)
202-
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable()
203-
{
204-
if constexpr (DMA1 == peripheral)
205-
{
194+
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable() {
195+
if constexpr (DMA1 == peripheral) {
206196
static_assert(channel <= DMA_CH4, "for DMA1, the channel is from DMA_CH0 to DMA_CH4");
207197
}
208198

209199
DMA_CHCTL(peripheral, channel) &= static_cast<uint32_t>(~nSource);
210200
}
211201
#elif defined(GD32F20X)
212-
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable()
213-
{
202+
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable() {
214203
DMA_CHCTL(peripheral, channel) &= static_cast<uint32_t>(~nSource);
215204
}
216205
#elif defined(GD32F4XX)
217-
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable()
218-
{
219-
if constexpr (DMA_CHXFCTL_FEEIE != nSource)
220-
{
206+
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable() {
207+
if constexpr (DMA_CHXFCTL_FEEIE != nSource) {
221208
DMA_CHCTL(peripheral, channel) &= static_cast<uint32_t>(~nSource);
222-
}
223-
else
224-
{
209+
} else {
225210
DMA_CHFCTL(peripheral, channel) &= static_cast<uint32_t>(~nSource);
226211
}
227212
}
228213
#elif defined(GD32H7XX)
229-
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable()
230-
{
231-
if constexpr (DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & nSource))
232-
{
214+
template <uint32_t peripheral, dma_channel_enum channel, uint32_t nSource> inline void Gd32DmaInterruptDisable() {
215+
if constexpr (DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & nSource)) {
233216
DMA_CHCTL(peripheral, channel) &= static_cast<uint32_t>(~nSource);
234-
}
235-
else
236-
{
217+
} else {
237218
DMA_CHFCTL(peripheral, channel) &= static_cast<uint32_t>(~DMA_CHXFCTL_FEEIE);
238219
DMA_CHCTL(peripheral, channel) &= static_cast<uint32_t>(~(nSource & (~DMA_CHXFCTL_FEEIE)));
239220
}

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