@@ -157,27 +157,27 @@ struct DirGpio {
157157} // namespace dmx
158158
159159static constexpr dmx::DirGpio kDirGpio [DMX_MAX_PORTS ] = {
160- {dmx::config::kDirPort0GpioPort , dmx::config::kDirPort0GpioPin },
160+ {. port = dmx::config::kDirPort0GpioPort , . pin = dmx::config::kDirPort0GpioPin },
161161#if DMX_MAX_PORTS >= 2
162- {dmx::config::kDirPort1GpioPort , dmx::config::kDirPort1GpioPin },
162+ {. port = dmx::config::kDirPort1GpioPort , . pin = dmx::config::kDirPort1GpioPin },
163163#endif
164164#if DMX_MAX_PORTS >= 3
165- {dmx::config::kDirPort2GpioPort , dmx::config::kDirPort2GpioPin },
165+ {. port = dmx::config::kDirPort2GpioPort , . pin = dmx::config::kDirPort2GpioPin },
166166#endif
167167#if DMX_MAX_PORTS >= 4
168- {dmx::config::kDirPort3GpioPort , dmx::config::kDirPort3GpioPin },
168+ {. port = dmx::config::kDirPort3GpioPort , . pin = dmx::config::kDirPort3GpioPin },
169169#endif
170170#if DMX_MAX_PORTS >= 5
171- {dmx::config::kDirPort4GpioPort , dmx::config::kDirPort4GpioPin },
171+ {. port = dmx::config::kDirPort4GpioPort , . pin = dmx::config::kDirPort4GpioPin },
172172#endif
173173#if DMX_MAX_PORTS >= 6
174- {dmx::config::kDirPort5GpioPort , dmx::config::kDirPort5GpioPin },
174+ {. port = dmx::config::kDirPort5GpioPort , . pin = dmx::config::kDirPort5GpioPin },
175175#endif
176176#if DMX_MAX_PORTS >= 7
177- {dmx::config::kDirPort6GpioPort , dmx::config::kDirPort6GpioPin },
177+ {. port = dmx::config::kDirPort6GpioPort , . pin = dmx::config::kDirPort6GpioPin },
178178#endif
179179#if DMX_MAX_PORTS == 8
180- {dmx::config::kDirPort7GpioPort , dmx::config::kDirPort7GpioPin },
180+ {. port = dmx::config::kDirPort7GpioPort , . pin = dmx::config::kDirPort7GpioPin },
181181#endif
182182};
183183
@@ -291,9 +291,9 @@ void IrqHandlerDmxRdmInput() {
291291 index++;
292292 rx_buffer.rdm .index = index;
293293
294- const auto * p = reinterpret_cast <volatile struct TRdmMessage *>(&rx_buffer.rdm .data [0 ]);
294+ const auto * data = reinterpret_cast <volatile struct TRdmMessage *>(&rx_buffer.rdm .data [0 ]);
295295
296- if ((index >= 24 ) && (index <= sizeof (struct TRdmMessage )) && (index == p ->message_length )) {
296+ if ((index >= 24 ) && (index <= sizeof (struct TRdmMessage )) && (index == data ->message_length )) {
297297 rx_buffer.state = dmx::TxRxState::kRdmChecksumh ;
298298 } else if (index > sizeof (struct TRdmMessage )) {
299299 rx_buffer.state = dmx::TxRxState::kIdle ;
@@ -1483,7 +1483,7 @@ void Dmx::ClearData(uint32_t port_index) {
14831483 assert (port_index < dmx::config::max::kPorts );
14841484
14851485 auto * data = &s_DmxTxBuffer[port_index].dmx .data [0 ];
1486- data->length = 513 ; // Including START Code
1486+ data->length = dmx:: kSlotsMax ; // Including START Code
14871487 __builtin_memset (data->data , 0 , dmx::buffer::kSize );
14881488}
14891489
@@ -1523,7 +1523,7 @@ void Dmx::FullOn() {
15231523 }
15241524
15251525 data->data [0 ] = dmx::kStartCode ;
1526- data->length = 513 ;
1526+ data->length = dmx:: kSlotsMax ;
15271527
15281528 DataEnable (port_index);
15291529 }
@@ -1952,9 +1952,9 @@ void Dmx::Sync() {
19521952// DMX Receive
19531953const uint8_t * Dmx::GetDmxChanged ([[maybe_unused]] uint32_t port_index) {
19541954#if !defined(CONFIG_DMX_TRANSMIT_ONLY)
1955- const auto * __restrict__ p = GetDmxAvailable (port_index);
1955+ const auto * __restrict__ available = GetDmxAvailable (port_index);
19561956
1957- if (p == nullptr ) {
1957+ if (available == nullptr ) {
19581958 return nullptr ;
19591959 }
19601960
@@ -1968,7 +1968,7 @@ const uint8_t* Dmx::GetDmxChanged([[maybe_unused]] uint32_t port_index) {
19681968 dst32[i] = src32[i];
19691969 }
19701970
1971- return p ;
1971+ return available ;
19721972 }
19731973
19741974 bool is_changed = false ;
@@ -1983,7 +1983,7 @@ const uint8_t* Dmx::GetDmxChanged([[maybe_unused]] uint32_t port_index) {
19831983 }
19841984 }
19851985
1986- return (is_changed ? p : nullptr );
1986+ return (is_changed ? available : nullptr );
19871987#else
19881988 return nullptr ;
19891989#endif
@@ -2073,19 +2073,19 @@ const uint8_t* Dmx::RdmReceive(uint32_t port_index) {
20732073 if (data[0 ] == E120_SC_RDM ) {
20742074 const auto * rdm_command = reinterpret_cast <const struct TRdmMessage *>(data);
20752075
2076- uint32_t i ;
2076+ uint32_t index ;
20772077 uint16_t checksum = 0 ;
20782078
2079- for (i = 0 ; i < 24 ; i ++) {
2080- checksum = static_cast <uint16_t >(checksum + data[i ]);
2079+ for (index = 0 ; index < 24 ; index ++) {
2080+ checksum = static_cast <uint16_t >(checksum + data[index ]);
20812081 }
20822082
2083- for (; i < rdm_command->message_length ; i ++) {
2084- checksum = static_cast <uint16_t >(checksum + data[i ]);
2083+ for (; index < rdm_command->message_length ; index ++) {
2084+ checksum = static_cast <uint16_t >(checksum + data[index ]);
20852085 }
20862086
2087- if (data[i ++] == static_cast <uint8_t >(checksum >> 8 )) {
2088- if (data[i ] == static_cast <uint8_t >(checksum)) {
2087+ if (data[index ++] == static_cast <uint8_t >(checksum >> 8 )) {
2088+ if (data[index ] == static_cast <uint8_t >(checksum)) {
20892089#if !defined(CONFIG_DMX_DISABLE_STATISTICS)
20902090 sv_total_statistics[port_index].rdm .received .good = sv_total_statistics[port_index].rdm .received .good + 1 ;
20912091#endif
@@ -2106,17 +2106,19 @@ const uint8_t* Dmx::RdmReceive(uint32_t port_index) {
21062106}
21072107
21082108// RDM Receive with timeout
2109- const uint8_t * Dmx::RdmReceiveTimeOut (uint32_t port_index, uint16_t time_out) {
2109+ // NOLINTNEXTLINE(bugprone-easily-swappable-parameters)
2110+ const uint8_t * Dmx::RdmReceiveTimeOut (uint32_t port_index, uint16_t timeout_ms) {
21102111 DMX_CHECK_PORT_INDEX_PTR (port_index);
21112112
2112- uint8_t * p = nullptr ;
2113+ uint8_t * data_available = nullptr ;
21132114 TIMER_CNT (TIMER5 ) = 0 ;
21142115
21152116 do {
2116- if ((p = const_cast <uint8_t *>(RdmReceive (port_index))) != nullptr ) {
2117- return p;
2117+ data_available = const_cast <uint8_t *>(RdmReceive (port_index));
2118+ if (data_available != nullptr ) {
2119+ return data_available;
21182120 }
2119- } while (TIMER_CNT (TIMER5 ) < time_out );
2121+ } while (TIMER_CNT (TIMER5 ) < timeout_ms );
21202122
21212123 return nullptr ;
21222124}
@@ -2223,26 +2225,26 @@ void Dmx::SetTransmitPeriodTime(uint32_t period) {
22232225 }
22242226 }
22252227
2226- auto package_length_micro_seconds = s_dmx_transmit.break_time + s_dmx_transmit.mab_time + (length_max * 44U );
2228+ auto package_length_micro_seconds = s_dmx_transmit.break_time + s_dmx_transmit.mab_time + (length_max * dmx:: kSlotTime );
22272229
22282230 // The GD32F4xx/GD32H7XX Timer 1 has a 32-bit counter
22292231#if defined(GD32F4XX) || defined(GD32H7XX)
22302232#else
2231- if (package_length_micro_seconds > (static_cast < uint16_t >(~ 0 ) - 44U )) {
2233+ if (package_length_micro_seconds > (UINT16_MAX - dmx:: kSlotTime )) {
22322234 s_dmx_transmit.break_time = std::min (dmx::transmit::kBreakTimeTypical , s_dmx_transmit.break_time );
22332235 s_dmx_transmit.mab_time = dmx::transmit::kMabTimeMin ;
2234- package_length_micro_seconds = s_dmx_transmit.break_time + s_dmx_transmit.mab_time + (length_max * 44U );
2236+ package_length_micro_seconds = s_dmx_transmit.break_time + s_dmx_transmit.mab_time + (length_max * dmx:: kSlotTime );
22352237 }
22362238#endif
22372239
22382240 if (period != 0 ) {
22392241 if (period < package_length_micro_seconds) {
2240- transmit_period_ = std::max (dmx::transmit::kBreakToBreakTimeMin , package_length_micro_seconds + 44U );
2242+ transmit_period_ = std::max (dmx::transmit::kBreakToBreakTimeMin , package_length_micro_seconds + dmx:: kSlotTime );
22412243 } else {
22422244 transmit_period_ = period;
22432245 }
22442246 } else {
2245- transmit_period_ = std::max (dmx::transmit::kBreakToBreakTimeMin , package_length_micro_seconds + 44U );
2247+ transmit_period_ = std::max (dmx::transmit::kBreakToBreakTimeMin , package_length_micro_seconds + dmx:: kSlotTime );
22462248 }
22472249
22482250 s_dmx_transmit.inter_time = transmit_period_ - package_length_micro_seconds;
@@ -2308,7 +2310,7 @@ dmx::OutputStyle Dmx::GetOutputStyle(uint32_t port_index) const {
23082310
23092311// Setup
23102312static void UartDmxConfig (uint32_t usart_periph) {
2311- Gd32UartBegin (usart_periph, 250000U , gd32::kUartBits8 , gd32::kUartParityNone , gd32::kUartStop2Bits );
2313+ Gd32UartBegin (usart_periph, dmx:: kBaudRate , gd32::kUartBits8 , gd32::kUartParityNone , gd32::kUartStop2Bits );
23122314}
23132315
23142316static void UsartDmaConfig () {
@@ -2710,7 +2712,7 @@ Dmx::Dmx() {
27102712
27112713 s_dmx_transmit.break_time = dmx::transmit::kBreakTimeTypical ;
27122714 s_dmx_transmit.mab_time = dmx::transmit::kMabTimeMin ;
2713- s_dmx_transmit.inter_time = dmx::transmit::kPeriodDefault - s_dmx_transmit.break_time - s_dmx_transmit.mab_time - (dmx::kChannelsMax * 44 ) - 44 ;
2715+ s_dmx_transmit.inter_time = dmx::transmit::kPeriodDefault - s_dmx_transmit.break_time - s_dmx_transmit.mab_time - (dmx::kChannelsMax * dmx:: kSlotTime ) - dmx:: kSlotTime ;
27142716
27152717 for (uint32_t port_index = 0 ; port_index < DMX_MAX_PORTS ; port_index++) {
27162718 Gd32GpioFsel (kDirGpio [port_index].port , kDirGpio [port_index].pin , GPIO_FSEL_OUTPUT );
@@ -2735,42 +2737,42 @@ Dmx::Dmx() {
27352737 Timer4Config (); // DMX Transmit -> UART4, USART5, UART6, UART7
27362738#endif
27372739
2738- #if defined(DMX_USE_USART0)
2740+ #if defined(DMX_USE_USART0) || defined(DMX_USE_USART0_RX)
27392741 UartDmxConfig (USART0 );
27402742 NVIC_SetPriority (USART0_IRQn, 0 );
27412743 NVIC_EnableIRQ (USART0_IRQn);
27422744#endif
2743- #if defined(DMX_USE_USART1)
2745+ #if defined(DMX_USE_USART1) || defined(DMX_USE_USART1_RX)
27442746 UartDmxConfig (USART1 );
27452747 NVIC_SetPriority (USART1_IRQn, 0 );
27462748 NVIC_EnableIRQ (USART1_IRQn);
27472749#endif
2748- #if defined(DMX_USE_USART2)
2750+ #if defined(DMX_USE_USART2) || defined(DMX_USE_USART2_RX)
27492751 UartDmxConfig (USART2 );
27502752 NVIC_SetPriority (USART2_IRQn, 0 );
27512753 NVIC_EnableIRQ (USART2_IRQn);
27522754#endif
2753- #if defined(DMX_USE_UART3)
2755+ #if defined(DMX_USE_UART3) || defined(DMX_USE_UART3_RX)
27542756 UartDmxConfig (UART3 );
27552757 NVIC_SetPriority (UART3_IRQn, 0 );
27562758 NVIC_EnableIRQ (UART3_IRQn);
27572759#endif
2758- #if defined(DMX_USE_UART4)
2760+ #if defined(DMX_USE_UART4) || defined(DMX_USE_UART4_RX)
27592761 UartDmxConfig (UART4 );
27602762 NVIC_SetPriority (UART4_IRQn, 0 );
27612763 NVIC_EnableIRQ (UART4_IRQn);
27622764#endif
2763- #if defined(DMX_USE_USART5)
2765+ #if defined(DMX_USE_USART5) || defined(DMX_USE_USART5_RX)
27642766 UartDmxConfig (USART5 );
27652767 NVIC_SetPriority (USART5_IRQn, 0 );
27662768 NVIC_EnableIRQ (USART5_IRQn);
27672769#endif
2768- #if defined(DMX_USE_UART6)
2770+ #if defined(DMX_USE_UART6) || defined(DMX_USE_UART6_RX)
27692771 UartDmxConfig (UART6 );
27702772 NVIC_SetPriority (UART6_IRQn, 0 );
27712773 NVIC_EnableIRQ (UART6_IRQn);
27722774#endif
2773- #if defined(DMX_USE_UART7)
2775+ #if defined(DMX_USE_UART7) || defined(DMX_USE_UART7_RX)
27742776 UartDmxConfig (UART7 );
27752777 NVIC_SetPriority (UART7_IRQn, 0 );
27762778 NVIC_EnableIRQ (UART7_IRQn);
0 commit comments