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Update GD32F20x peripheral library to v3.0.0
Syncs the GD32F20x standard peripheral driver set from V2.5.0 to V3.0.0, including updated file metadata and broad driver-level fixes. The update corrects register definitions and typos (notably in CAN), refactors DAC APIs/macros to the newer channel-based interface, and adds/adjusts APIs such as SPI format-error clearing and IRQ typing in MISC. It also improves robustness across multiple modules by tightening status/flag handling, adding timeout-aware error paths, and converting several previously unconditional returns/loops into explicit success/error flows. ENET, FWDGT, CAU/HAU, FMC, and other peripherals received behavioral and consistency updates aligned with the newer upstream driver release.
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Lines changed: 1173 additions & 972 deletions

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‎lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_adc.h‎

Lines changed: 2 additions & 2 deletions
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@@ -2,11 +2,11 @@
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\file gd32f20x_adc.h
33
\brief definitions for the ADC
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\version 2023-06-30, V2.5.0, firmware for GD32F20x
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\version 2026-02-06, V3.0.0, firmware for GD32F20x
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*/
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/*
9-
Copyright (c) 2023, GigaDevice Semiconductor Inc.
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Copyright (c) 2026, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:

‎lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_bkp.h‎

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@@ -2,11 +2,11 @@
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\file gd32f20x_bkp.h
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\brief definitions for the BKP
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\version 2023-06-30, V2.5.0, firmware for GD32F20x
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\version 2026-02-06, V3.0.0, firmware for GD32F20x
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*/
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/*
9-
Copyright (c) 2023, GigaDevice Semiconductor Inc.
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Copyright (c) 2026, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:

‎lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_can.h‎

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@@ -2,11 +2,11 @@
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\file gd32f20x_can.h
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\brief definitions for the CAN
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\version 2023-06-30, V2.5.0, firmware for GD32F20x
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\version 2026-02-06, V3.0.0, firmware for GD32F20x
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*/
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/*
9-
Copyright (c) 2023, GigaDevice Semiconductor Inc.
9+
Copyright (c) 2026, GigaDevice Semiconductor Inc.
1010
1111
Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
@@ -98,7 +98,7 @@ OF SUCH DAMAGE.
9898
#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */
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#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */
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#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */
101-
#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */
101+
#define CAN_F23DATA0(canx) REG32((canx) + 0x000002F8U) /*!< CAN filter 23 data 0 register */
102102
#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */
103103
#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */
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#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */
@@ -120,7 +120,7 @@ OF SUCH DAMAGE.
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#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */
121121
#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */
122122
#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */
123-
#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */
123+
#define CAN_F17DATA1(canx) REG32((canx) + 0x000002CCU) /*!< CAN filter 17 data 1 register */
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#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */
125125
#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */
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#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */
@@ -392,7 +392,7 @@ typedef enum {
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CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
393393
} can_interrupt_flag_enum;
394394

395-
/* CAN initiliaze parameters structure */
395+
/* CAN initialize parameters structure */
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typedef struct {
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uint8_t working_mode; /*!< CAN working mode */
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uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
@@ -415,7 +415,7 @@ typedef struct {
415415
uint8_t tx_ft; /*!< type of frame, data or remote */
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uint8_t tx_dlen; /*!< data length */
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uint8_t tx_data[8]; /*!< transmit data */
418-
} can_trasnmit_message_struct;
418+
} can_transmit_message_struct;
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420420
/* CAN receive message structure */
421421
typedef struct {
@@ -450,7 +450,7 @@ typedef enum {
450450
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
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CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
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CAN_ERROR_CRC, /*!< CRC error */
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CAN_ERROR_SOFTWARECFG, /*!< software configure */
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CAN_ERROR_SOFTWARECFG, /*!< software configuration */
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} can_error_enum;
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/* transmit states */
@@ -462,7 +462,7 @@ typedef enum {
462462
} can_transmit_state_enum;
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464464
typedef enum {
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CAN_INIT_STRUCT = 0, /* CAN initialize parameters struct */
465+
CAN_INIT_STRUCT = 0U, /* CAN initialize parameters struct */
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CAN_FILTER_STRUCT, /* CAN filter parameters struct */
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CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
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CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
@@ -586,7 +586,7 @@ typedef enum {
586586
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
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#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
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589-
/* CAN resynchronisation jump width */
589+
/* CAN resynchronization jump width */
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#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
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#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
592592
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
@@ -663,6 +663,9 @@ typedef enum {
663663
/* CAN timeout */
664664
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
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666+
/* CAN mailbox empty status mask */
667+
#define CAN_ALL_MAILBOX_EMPTY ((uint32_t)0x1C000000U) /*!< CAN mailbox empty status mask */
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/* interrupt enable bits */
667670
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
668671
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
@@ -705,11 +708,11 @@ void can_time_trigger_mode_disable(uint32_t can_periph);
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706709
/* transmit functions */
707710
/* transmit CAN message */
708-
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message);
711+
uint8_t can_message_transmit(uint32_t can_periph, can_transmit_message_struct *transmit_message);
709712
/* get CAN transmit state */
710713
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
711714
/* stop CAN transmission */
712-
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
715+
ErrStatus can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
713716
/* CAN receive message */
714717
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
715718
/* CAN release FIFO */

‎lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_cau.h‎

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@@ -2,11 +2,11 @@
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\file gd32f20x_cau.h
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\brief definitions for the CAU
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\version 2023-06-30, V2.5.0, firmware for GD32F20x
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\version 2026-02-06, V3.0.0, firmware for GD32F20x
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*/
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/*
9-
Copyright (c) 2023, GigaDevice Semiconductor Inc.
9+
Copyright (c) 2026, GigaDevice Semiconductor Inc.
1010
1111
Redistribution and use in source and binary forms, with or without modification,
1212
are permitted provided that the following conditions are met:
@@ -182,8 +182,8 @@ typedef struct {
182182
#define CAU_INT_OUTFIFO CAU_INTEN_OINTEN /*!< OUT FIFO Interrupt */
183183

184184
/* cau_stat1 register value */
185-
#define CAU_FLAG_INFIFO (CAU_STAT1_ISTA | ((uint32_t)0x00000020U)) /*!< IN FIFO flag status */
186-
#define CAU_FLAG_OUTFIFO (CAU_STAT1_OSTA | ((uint32_t)0x00000020U)) /*!< OUT FIFO flag status */
185+
#define CAU_FLAG_INFIFO (CAU_STAT1_ISTA | BIT(31)) /*!< IN FIFO flag status */
186+
#define CAU_FLAG_OUTFIFO (CAU_STAT1_OSTA | BIT(31)) /*!< OUT FIFO flag status */
187187

188188
/* cau_intf register value */
189189
#define CAU_INT_FLAG_INFIFO CAU_INTF_IINTF /*!< IN FIFO interrupt status */

‎lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_crc.h‎

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@@ -2,11 +2,11 @@
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\file gd32f20x_crc.h
33
\brief definitions for the CRC
44
5-
\version 2023-06-30, V2.5.0, firmware for GD32F20x
5+
\version 2026-02-06, V3.0.0, firmware for GD32F20x
66
*/
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/*
9-
Copyright (c) 2023, GigaDevice Semiconductor Inc.
9+
Copyright (c) 2026, GigaDevice Semiconductor Inc.
1010
1111
Redistribution and use in source and binary forms, with or without modification,
1212
are permitted provided that the following conditions are met:

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