Enable DMA1 Ch3/4 IRQ for GD32F30X

Add NVIC_SetPriority/NVIC_EnableIRQ for DMA1_Channel3_Channel4_IRQn when building for GD32F30X. Previously the code only handled DMA1_Channel4_IRQn for non-GD32F4XX targets; this change ensures the correct IRQ is enabled for the GD32F30X DMA channel mapping while preserving the existing non-F4XX and F4XX branches.

Author: vanvught

lib-dmx/src/gd32/dmx.cpp

@@ -2450,7 +2450,10 @@ static void UsartDmaConfig() {
     dma_channel_subperipheral_select(UART3_DMAx, UART3_TX_DMA_CHx, UART3_TX_DMA_SUBPERIx);
 #endif
     Gd32DmaInterruptDisable<UART3_DMAx, UART3_TX_DMA_CHx, DMA_INTERRUPT_DISABLE>();
-#if !defined(GD32F4XX)
+#if defined(GD32F30X)
+    NVIC_SetPriority(DMA1_Channel3_Channel4_IRQn, 1);
+    NVIC_EnableIRQ(DMA1_Channel3_Channel4_IRQn);
+#elif !defined(GD32F4XX)
     NVIC_SetPriority(DMA1_Channel4_IRQn, 1);
     NVIC_EnableIRQ(DMA1_Channel4_IRQn);
 #else