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dgarskedgarske
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Add wolfBoot target for Infineon PSOC Edge E8
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‎.github/workflows/test-configs.yml‎

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arch: arm
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config-file: ./config/examples/stm32c5.config
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psoc_e8_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/psoc_e8_ai.config
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psoc_e8_wolfcrypt_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/psoc_e8_ai.config
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make-args: WOLFCRYPT_TEST=1 WOLFCRYPT_BENCHMARK=1
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# wolfBoot linked into RRAM, partitions still in QSPI.
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psoc_e8_rram_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/psoc_e8_ai.config
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make-args: PSOC_E8_BOOT_RRAM=1
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psoc_c3_test:
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uses: ./.github/workflows/test-build.yml
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with:

‎arch.mk‎

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CFLAGS+=-DPSOC_C3_I2C_HSIOM_SEL=$(PSOC_C3_I2C_HSIOM_SEL)
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CFLAGS+=-DPSOC_C3_I2C_HZ=$(PSOC_C3_I2C_HZ)
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endif
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ifeq ($(TARGET),psoc_e8)
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CORTEX_M33=1
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CFLAGS+=-Ihal
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# Extended boot runs the first CM33 image in place, after a 0x400 MCUboot
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# header: from QSPI by default, or from RRAM with PSOC_E8_BOOT_RRAM=1
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# (needs the boot policy reprovisioned). ARCH_FLASH_OFFSET is the slot.
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PSOC_E8_BOOT_RRAM?=0
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ifeq ($(PSOC_E8_BOOT_RRAM),1)
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PSOC_E8_RRAM_SLOT_SIZE?=0x20000
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ARCH_FLASH_OFFSET=0x12011000
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WOLFBOOT_ORIGIN=0x12011400
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BOOTLOADER_PARTITION_SIZE=$$(( $(PSOC_E8_RRAM_SLOT_SIZE) - 0x400))
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else
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ARCH_FLASH_OFFSET=0x18100000
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WOLFBOOT_ORIGIN=0x18100400
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BOOTLOADER_PARTITION_SIZE=$$(( $(WOLFBOOT_PARTITION_BOOT_ADDRESS) - $(WOLFBOOT_ORIGIN)))
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endif
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LSCRIPT_IN=hal/$(TARGET).ld
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# Board wiring, defaulted for KIT_PSE84_AI.
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PSOC_E8_UART_SCB?=2
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PSOC_E8_UART_PORT?=6
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PSOC_E8_UART_RX_PIN?=5
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PSOC_E8_UART_TX_PIN?=7
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PSOC_E8_UART_HSIOM_SEL?=20
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PSOC_E8_UART_PCLK_GR?=1
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PSOC_E8_UART_PCLK_IDX?=1
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PSOC_E8_PCLK_HZ?=100000000
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PSOC_E8_QSPI_SECTOR_SIZE?=0x40000
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PSOC_E8_CPU_HZ?=200000000
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CFLAGS+=-DPSOC_E8_UART_SCB=$(PSOC_E8_UART_SCB)
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CFLAGS+=-DPSOC_E8_UART_PORT=$(PSOC_E8_UART_PORT)
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CFLAGS+=-DPSOC_E8_UART_RX_PIN=$(PSOC_E8_UART_RX_PIN)
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CFLAGS+=-DPSOC_E8_UART_TX_PIN=$(PSOC_E8_UART_TX_PIN)
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CFLAGS+=-DPSOC_E8_UART_HSIOM_SEL=$(PSOC_E8_UART_HSIOM_SEL)
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CFLAGS+=-DPSOC_E8_UART_PCLK_GR=$(PSOC_E8_UART_PCLK_GR)
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CFLAGS+=-DPSOC_E8_UART_PCLK_IDX=$(PSOC_E8_UART_PCLK_IDX)
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CFLAGS+=-DPSOC_E8_PCLK_HZ=$(PSOC_E8_PCLK_HZ)
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CFLAGS+=-DPSOC_E8_QSPI_SECTOR_SIZE=$(PSOC_E8_QSPI_SECTOR_SIZE)
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CFLAGS+=-DPSOC_E8_CPU_HZ=$(PSOC_E8_CPU_HZ)
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endif
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ifeq ($(TARGET),m2354)
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CORTEX_M23=1
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CFLAGS+=-Ihal

‎config/examples/psoc_e8_ai.config‎

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ARCH?=ARM
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TARGET?=psoc_e8
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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CORTEX_M33?=1
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TZEN?=0
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NO_ASM?=0
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NO_MPU=1
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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# The QSPI NOR rejects a second program into a 16-byte ECC unit.
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=1
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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DEBUG_UART=1
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# Keeps the application vector table 1 KB aligned.
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IMAGE_HEADER_SIZE?=1024
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# KIT_PSE84_AI: 64 MB QSPI NOR, 256 KB sectors, Secure code-bus alias.
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#
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# 0x18100000 - 0x1813FFFF wolfBoot slot: 0x400 MCUboot header + wolfBoot
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# 0x18140000 - 0x1823FFFF BOOT (1 MB)
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# 0x18240000 - 0x1833FFFF UPDATE (1 MB)
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# 0x18340000 - 0x1837FFFF SWAP (one sector)
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#
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# Board wiring: PSOC_E8_* make options in arch.mk, see docs/Targets.md.
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WOLFBOOT_SECTOR_SIZE?=0x40000
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WOLFBOOT_PARTITION_SIZE?=0x100000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x18140000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x18240000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x18340000

‎docs/Targets.md‎

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* [Cortex-A72 / Raspberry Pi Compute Module 4](#cortex-a72--raspberry-pi-compute-module-4-bcm2711)
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* [Cypress PSoC-6](#cypress-psoc-6)
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* [Infineon PSOC Control C3](#infineon-psoc-control-c3)
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* [Infineon PSOC Edge E8](#infineon-psoc-edge-e8)
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* [Infineon AURIX TC3xx](#infineon-aurix-tc3xx)
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* [Infineon AURIX TC4xx](#infineon-aurix-tc4xx)
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* [Intel x86-64 Intel FSP](#intel-x86_64-with-intel-fsp-support)
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Every FIFO and bus wait in both drivers is bounded, so a device that is absent or unpowered makes `wolfBoot_tpm2_init()` report a failure rather than wedging the bootloader in a spin loop.
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## Infineon PSOC Edge E8
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The Infineon PSOC Edge E8 family (PSE8x, CAT1D) pairs a Cortex-M33 with TrustZone and a Cortex-M55 behind a Secure Enclave, which runs the boot ROM and Infineon's extended boot. wolfBoot runs on the CM33 in the Secure state as the first image extended boot launches. The port is bare metal and needs no Peripheral Driver Library or BSP. Board differences are make options, and `config/examples/psoc_e8_ai.config` describes KIT_PSE84_AI.
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Verified on KIT_PSE84_AI (PSE846GPS2DBZC4A): boot from QSPI under the factory extended boot, ECC256 verification and handoff, A/B update with confirmation, resumption of an update interrupted mid-swap, RRAM write and erase, and the wolfCrypt test and benchmark. Booting from RRAM (`PSOC_E8_BOOT_RRAM=1`) is build-tested only. The CM55 is not started.
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### Boot chain and memory
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Extended boot runs the first CM33 image in place from QSPI at `0x60100000`, in MCUboot format: a 0x400-byte header, the image, and a TLV with the SHA-256 of both, with no key. `tools/scripts/psoc_e8/psoc_e8_mcuboot_wrap.py` wraps `wolfboot.bin` this way.
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Each memory has four aliases, Secure/Non-secure by code/system bus. wolfBoot links at `0x18100400` and all `.config` addresses use the Secure code-bus QSPI alias:
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```
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RRAM 0x02000000 NS code 0x12000000 S code 0x22000000 NS sys 0x32000000 S sys
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QSPI 0x08000000 NS code 0x18000000 S code 0x60000000 NS sys 0x70000000 S sys
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0x18100000 - 0x1813FFFF wolfBoot slot (MCUboot header + wolfBoot)
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0x18140000 - 0x1823FFFF BOOT partition (1 MB)
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0x18240000 - 0x1833FFFF UPDATE partition (1 MB)
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0x18340000 - 0x1837FFFF SWAP sector (256 KB)
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```
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`IMAGE_HEADER_SIZE=1024` keeps the application vector table on the 1 KB boundary the CM33 requires.
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### QSPI flash
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The HAL programs the 64 MB NOR through the SMIF MMIO command interface, using the device and 3- or 4-byte addressing that extended boot configured for XIP, which stays enabled. The flash path runs from RAM with interrupts masked, stages each page in RAM (the source is often QSPI itself), and invalidates the SMIF and CM33 caches afterwards. The test application runs from the QSPI it programs, so its flash path is also placed in RAM.
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The NOR keeps ECC over 16-byte units and rejects a second program into a unit, so the config sets `NVM_FLASH_WRITEONCE=1`. With 256 KB sectors this costs a sector-sized RAM buffer. A rejected program leaves the part busy across a warm reset, where extended boot can no longer read it, so the HAL clears the failure flags when it sees them.
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### Build options
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wolfBoot does not change the clocks extended boot sets. The console is SCB2 on P6.5/P6.7, the KitProg3 COM port, at 115200 baud.
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| Option | Default | Purpose |
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| --- | --- | --- |
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| `PSOC_E8_UART_SCB` | 2 | console SCB instance |
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| `PSOC_E8_UART_PORT` / `_RX_PIN` / `_TX_PIN` | 6 / 5 / 7 | console pins |
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| `PSOC_E8_UART_HSIOM_SEL` | 20 | HSIOM selector for the UART |
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| `PSOC_E8_UART_PCLK_GR` / `_IDX` | 1 / 1 | console peripheral clock group and index |
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| `PSOC_E8_PCLK_HZ` | 100000000 | CLK_HF10, feeding that group |
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| `PSOC_E8_CPU_HZ` | 200000000 | CLK_HF0, test-app benchmark time base |
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| `PSOC_E8_QSPI_SECTOR_SIZE` | 0x40000 | QSPI erase sector |
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| `PSOC_E8_BOOT_RRAM` | 0 | link wolfBoot into RRAM instead of QSPI |
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| `PSOC_E8_RRAM_SLOT_SIZE` | 0x20000 | RRAM slot with `PSOC_E8_BOOT_RRAM=1` |
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### Building and flashing
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```sh
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cp config/examples/psoc_e8_ai.config .config
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make clean && make
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tools/scripts/psoc_e8/psoc_e8_flash.sh
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```
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The script wraps `wolfboot.bin` and programs it and `test-app/image_v1_signed.bin` over the KitProg3, with the ModusToolbox Programming Tools OpenOCD (`MTB_PROGTOOLS`, default `/opt/Tools/ModusToolboxProgtools-1.6`). Set `KITPROG_SERIAL` if several probes are attached. This replaces the factory CM33 image, so read QSPI back first to keep the stock demo. `factory.bin` does not apply here, since it lacks the MCUboot header.
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To test an update, sign v2 and program it into UPDATE. The v1 application triggers the update, and v2 confirms itself:
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```sh
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IMAGE_HEADER_SIZE=1024 ./tools/keytools/sign --ecc256 --sha256 \
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test-app/image.bin wolfboot_signing_private_key.der 2
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tools/scripts/psoc_e8/psoc_e8_flash.sh --update test-app/image_v2_signed.bin
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```
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`make WOLFCRYPT_TEST=1 WOLFCRYPT_BENCHMARK=1` adds the software wolfCrypt test and benchmark to the test application. Its RNG seed is deterministic and only for testing.
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### Booting from RRAM
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`PSOC_E8_BOOT_RRAM=1` links wolfBoot at `0x12011400` in the RRAM user area, keeping the partitions in QSPI. Extended boot only launches it once the boot policy is reprovisioned with Infineon's Edge Protect Tools, which this port does not automate. RRAM is written in 16-byte blocks through the RRAMC indirect-write action, under the IPC and PC_LOCK locks. It has no erase, so `hal_flash_erase()` writes zeros.
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## Infineon AURIX TC3xx
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wolfBoot supports the Infineon AURIX TC3xx family and includes a demo application for the TC375 AURIX LiteKit-V2. It can be configured to run on either the TriCore application cores or the HSM core.

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