Bound remaining SDHCI waits and scope Agilex 5 command settle to init

Author: aidangarske

hal/agilex5.c

@@ -67,12 +67,14 @@ void uart_write(const char *buf, uint32_t len)
         if (buf[i] == '\n') {
             while (((UART_REG(UART_LSR) & UART_LSR_THRE) == 0U) &&
                     (--timeout != 0U)) {}
-            UART_REG(UART_THR) = '\r';
+            if (timeout != 0U)
+                UART_REG(UART_THR) = '\r';
             timeout = UART_TIMEOUT;
         }
         while (((UART_REG(UART_LSR) & UART_LSR_THRE) == 0U) &&
                 (--timeout != 0U)) {}
-        UART_REG(UART_THR) = (uint32_t)(uint8_t)buf[i];
+        if (timeout != 0U)
+            UART_REG(UART_THR) = (uint32_t)(uint8_t)buf[i];
     }
 }
 #else

include/sdhci.h

@@ -483,15 +483,11 @@ void sdhci_platform_init(void);
  * to the card clock and return that, keeping the internal divider ~1. */
 uint32_t sdhci_platform_set_clock(uint32_t clock_khz, uint32_t base_clk_khz);
 
-/* Preserve a host controller initialized by an earlier boot stage. */
-#ifndef SDHCI_SKIP_HOST_RESET
-#define SDHCI_SKIP_HOST_RESET 0
-#endif
+/* Preserve a host controller initialized by an earlier boot stage.
+ * Opt in with -DSDHCI_SKIP_HOST_RESET=1. */
 
-/* Optional controller settling time after each command. */
-#ifndef SDHCI_WAIT_AFTER_CMD_US
-#define SDHCI_WAIT_AFTER_CMD_US 0U
-#endif
+/* Optional controller settle time in microseconds after each init command.
+ * Opt in with -DSDHCI_WAIT_AFTER_CMD_US=<us>. */
 
 /* Platform interrupt setup (PLIC/NVIC/GIC/etc.) */
 void sdhci_platform_irq_init(void);

src/sdhci.c

@@ -585,6 +585,16 @@ static uint32_t sdhci_get_response_type(uint8_t resp_type)
 
 #define DEVICE_BUSY 1
 
+/* When an earlier boot stage owns the controller (skip host reset), engage
+ * per-command line-reset recovery; the other targets still soft-reset at init. */
+#if defined(SDHCI_SKIP_HOST_RESET) && ((SDHCI_SKIP_HOST_RESET + 0) != 0)
+#define SDHCI_SKIP_HOST_RESET_ENABLED
+#endif
+
+/* Set only while sdhci_init() runs the card-identification sequence. */
+static int sdhci_in_init = 0;
+
+#ifdef SDHCI_SKIP_HOST_RESET_ENABLED
 static int sdhci_reset_cmd_line(void)
 {
     uint32_t timeout = 0x000FFFFF;
@@ -595,6 +605,7 @@ static int sdhci_reset_cmd_line(void)
 
     return (timeout > 0U) ? 0 : -1;
 }
+#endif
 
 static int sdhci_send_cmd_internal(uint32_t cmd_type,
     uint32_t cmd_index, uint32_t cmd_arg, uint8_t resp_type)
@@ -609,7 +620,16 @@ static int sdhci_send_cmd_internal(uint32_t cmd_type,
 #endif
 
     /* wait for command line to be idle */
-    while ((SDHCI_REG(SDHCI_SRS09) & SDHCI_SRS09_CICMD) != 0);
+    while (((SDHCI_REG(SDHCI_SRS09) & SDHCI_SRS09_CICMD) != 0U) &&
+            (--timeout > 0U)) {}
+    if (timeout == 0U) {
+        wolfBoot_printf("sdhci_send_cmd: command inhibit timeout on entry\n");
+#ifdef SDHCI_SKIP_HOST_RESET_ENABLED
+        if (sdhci_reset_cmd_line() != 0)
+            wolfBoot_printf("sdhci_send_cmd: command line reset timeout\n");
+#endif
+    }
+    timeout = 0x000FFFFF;
 
     /* set command argument and command transfer registers */
     SDHCI_REG_SET(SDHCI_SRS02, cmd_arg);
@@ -635,8 +655,10 @@ static int sdhci_send_cmd_internal(uint32_t cmd_type,
             "error SRS12=0x%08X\n",
             cmd_index, cmd_arg, resp_type, SDHCI_REG(SDHCI_SRS12));
         status = -1; /* error */
+#ifdef SDHCI_SKIP_HOST_RESET_ENABLED
         if (sdhci_reset_cmd_line() != 0)
             wolfBoot_printf("sdhci_send_cmd: command line reset timeout\n");
+#endif
     }
 
     SDHCI_REG_SET(SDHCI_SRS12, SDHCI_SRS12_CC); /* clear command complete */
@@ -646,8 +668,10 @@ static int sdhci_send_cmd_internal(uint32_t cmd_type,
     if (timeout == 0U) {
         wolfBoot_printf("sdhci_send_cmd: command inhibit timeout\n");
         status = -1;
+#ifdef SDHCI_SKIP_HOST_RESET_ENABLED
         if (sdhci_reset_cmd_line() != 0)
             wolfBoot_printf("sdhci_send_cmd: command line reset timeout\n");
+#endif
     }
 
     if (status == 0) {
@@ -661,8 +685,11 @@ static int sdhci_send_cmd_internal(uint32_t cmd_type,
         }
     }
 
-#if SDHCI_WAIT_AFTER_CMD_US > 0U
-    udelay(SDHCI_WAIT_AFTER_CMD_US);
+#if defined(SDHCI_WAIT_AFTER_CMD_US) && ((SDHCI_WAIT_AFTER_CMD_US + 0) != 0)
+    /* Cadence controllers need a settle window after the card-init sequence;
+     * confine it to init so bulk data commands do not pay it per block. */
+    if (sdhci_in_init != 0)
+        udelay(SDHCI_WAIT_AFTER_CMD_US);
 #endif
 
     return status;
@@ -744,8 +771,13 @@ void sdhci_shutdown(void)
 /* Reset data and command lines to recover from errors */
 static inline void sdhci_reset_lines(void)
 {
+    uint32_t timeout = 0x000FFFFF;
+
     sdhci_reg_or(SDHCI_SRS11, SDHCI_SRS11_RESET_DAT_CMD);
-    while (SDHCI_REG(SDHCI_SRS11) & SDHCI_SRS11_RESET_DAT_CMD);
+    while (((SDHCI_REG(SDHCI_SRS11) & SDHCI_SRS11_RESET_DAT_CMD) != 0U) &&
+            (--timeout > 0U)) {}
+    if (timeout == 0U)
+        wolfBoot_printf("sdhci_reset_lines: reset timeout\n");
 }
 
 /* ============================================================================
@@ -836,6 +868,10 @@ static int sdcard_power_init_seq(uint32_t voltage)
         }
         if (status != 0) {
             wolfBoot_printf("SD: CMD8 failed after %d retries\n", retries);
+            wolfBoot_printf("SD: SRS09=0x%08X SRS10=0x%08X SRS11=0x%08X "
+                "SRS15=0x%08X\n",
+                SDHCI_REG(SDHCI_SRS09), SDHCI_REG(SDHCI_SRS10),
+                SDHCI_REG(SDHCI_SRS11), SDHCI_REG(SDHCI_SRS15));
         }
         else if (retries > 0) {
             wolfBoot_printf("SD: CMD8 succeeded after %d retries\n", retries);
@@ -1748,6 +1784,19 @@ static int sdhci_transfer(int dir, uint32_t cmd_index, uint32_t block_addr,
     return status;
 }
 
+static int sdhci_init_internal(void);
+
+int sdhci_init(void)
+{
+    int status;
+
+    sdhci_in_init = 1;
+    status = sdhci_init_internal();
+    sdhci_in_init = 0;
+
+    return status;
+}
+
 /* Public API: Read from MMC/SD card */
 int sdhci_read(uint32_t cmd_index, uint32_t block_addr, uint32_t* dst, uint32_t sz)
 {
@@ -1764,7 +1813,7 @@ int sdhci_write(uint32_t cmd_index, uint32_t block_addr, const uint32_t* src, ui
  * Controller Initialization
  * ============================================================================ */
 
-int sdhci_init(void)
+static int sdhci_init_internal(void)
 {
     int status = 0;
     uint32_t reg, cap;
@@ -1785,7 +1834,7 @@ int sdhci_init(void)
      * not be ready to accept register writes on some platforms. */
     udelay(1000); /* 1ms */
 
-#if SDHCI_SKIP_HOST_RESET == 0
+#ifndef SDHCI_SKIP_HOST_RESET_ENABLED
     /* Reset the host controller unless an earlier boot stage initialized it. */
     sdhci_reg_or(SDHCI_HRS00, SDHCI_HRS00_SWR);
     /* Bit will clear when reset is done */