Make Agilex 5 console UART, DDR size and FDT node disables board configurable

Author: aidangarske

config/examples/agilex5_013b_sdcard.config

@@ -49,6 +49,11 @@ CFLAGS_EXTRA+=-DBOOT_PART_A=1 -DBOOT_PART_B=2
 CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000
 CFLAGS_EXTRA+=-DLINUX_BOOTARGS_ROOT=\"/dev/mmcblk0p4\"
 
+# Board settings, see docs/Agilex5.md. Defaults match the 013B dev kit.
+#CFLAGS_EXTRA+=-DDEBUG_UART_NUM=1
+#CFLAGS_EXTRA+=-DAGILEX5_DDR_SIZE=0x70000000
+CFLAGS_EXTRA+=-DAGILEX5_FDT_DISABLE_PATHS=\"/leds\"
+
 # SD6HC uses SDMA for cache-coherent multi-block transfers.
 CFLAGS_EXTRA+=-DSDHCI_FORCE_CARD_DETECT
 

docs/Agilex5.md

@@ -36,6 +36,21 @@ Create the Linux FIT from the GSRD `Image` and the exact board DTB, then sign
 that FIT with wolfBoot's normal image-signing flow. Initialize both raw A/B
 partitions with a valid signed image for the first boot.
 
+### Board settings
+
+The example config targets the DK-A5E013BM16AEA. Other boards set these in
+their config:
+
+| Setting | Default | Purpose |
+|---|---|---|
+| `CFLAGS_EXTRA+=-DDEBUG_UART_NUM=1` | UART0 (`0x10C02000`) | console UART for wolfBoot and Linux `earlycon` |
+| `CFLAGS_EXTRA+=-DDEBUG_UART_BASE=<addr>` | unset | any other console UART; write the address without a `UL` suffix |
+| `CFLAGS_EXTRA+=-DAGILEX5_DDR_SIZE=<bytes>` | `0x70000000` (1792 MiB) | DDR size written to the DTB memory node |
+| `CFLAGS_EXTRA+=-DAGILEX5_FDT_DISABLE_PATHS=\"/leds\"` | unset | comma-separated DTB node paths to mark `disabled`, for hardware behind the unprogrammed FPGA |
+
+wolfBoot does not read the DDR size from the DTB, because without U-Boot the
+memory node holds whatever the DTB author wrote rather than the fitted size.
+
 The checked-in `hal/agilex5.its` is a minimal FIT example. A GSRD production
 image must use the GSRD-generated kernel load address and board DTB, then be
 signed with the deployment key. Do not place private keys in the source tree
@@ -72,7 +87,9 @@ software and is deliberately not linked into bare-metal wolfBoot.
    PSCI reboot, and rootfs `/dev/mmcblk0p4`.
 5. Build the complete WIC, inspect all four partitions, flash the whole card,
    compare the complete image span, cold boot, and test A-to-B fallback by
-   corrupting only a disposable copy of A.
+   corrupting only a disposable copy of A. Both slots must hold the same
+   version: with `ALLOW_DOWNGRADE=0` wolfBoot refuses to fall back to a lower
+   version (`Rollback to lower version not allowed`) and panics instead.
 6. From the booted WIC run `/usr/bin/wolfcrypttest`. Require exit zero and
    `ALTERA-FCS test passed!` to prove the Linux image still provides hardware
    FCS offload.

hal/agilex5.c

@@ -38,9 +38,11 @@
 #ifndef LINUX_BOOTARGS_ROOT
 #define LINUX_BOOTARGS_ROOT "/dev/mmcblk0p4"
 #endif
+#define AGILEX5_STR2(x) #x
+#define AGILEX5_STR(x) AGILEX5_STR2(x)
 #define LINUX_BOOTARGS \
-    "earlycon=uart8250,mmio32,0x10c02000 console=ttyS0,115200 " \
-    "root=" LINUX_BOOTARGS_ROOT " rootwait"
+    "earlycon=uart8250,mmio32," AGILEX5_STR(DEBUG_UART_BASE) \
+    " console=ttyS0,115200 root=" LINUX_BOOTARGS_ROOT " rootwait"
 #endif
 
 #ifdef DEBUG_UART
@@ -51,7 +53,8 @@
 #define UART_LSR_TEMT (1U << 6)
 #define UART_TIMEOUT 1000000U
 #define UART_REG(_n) \
-    (*(volatile uint32_t *)(AGILEX5_UART0_BASE + ((uintptr_t)(_n) << 2)))
+    (*(volatile uint32_t *)((uintptr_t)DEBUG_UART_BASE + \
+        ((uintptr_t)(_n) << 2)))
 
 void uart_init(void)
 {
@@ -153,11 +156,22 @@ void *hal_get_dts_update_address(void)
 }
 
 #ifdef __WOLFBOOT
+#ifdef AGILEX5_FDT_DISABLE_PATHS
+static const char* const agilex5_fdt_disable[] = { AGILEX5_FDT_DISABLE_PATHS };
+#endif
+
 int hal_dts_fixup(void *dts_addr, uint32_t capacity)
 {
     fdt_ctx ctx;
     int off;
     int ret;
+#ifdef AGILEX5_FDT_DISABLE_PATHS
+    unsigned int i;
+#endif
+
+    /* Bare-metal and RTOS payloads carry no DTB. */
+    if (dts_addr == NULL)
+        return 0;
 
     /* Validate the blob against the window it actually occupies. */
     ret = fdt_open(&ctx, dts_addr, capacity);
@@ -171,9 +185,6 @@ int hal_dts_fixup(void *dts_addr, uint32_t capacity)
         return ret;
     }
 
-    /* U-Boot normally patches the memory node after SPL has measured the
-     * LPDDR4.  wolfBoot bypasses U-Boot and passes this DTB directly to
-     * Linux, so preserve the board's 1792 MiB memory map explicitly. */
     off = fdt_find_devtype(&ctx, -1, "memory");
     if (off >= 0) {
         uint64_t reg[2];
@@ -190,19 +201,23 @@ int hal_dts_fixup(void *dts_addr, uint32_t capacity)
             (unsigned long)AGILEX5_DDR_SIZE);
     }
 
-    /* The board DT contains an optional FPGA-backed gpio-leds node.  The
-     * normal GSRD path programs the fabric in U-Boot before probing it; the
-     * direct wolfBoot handoff does not yet program that optional design.
-     * Keep Linux from touching an unconfigured fabric register while the
-     * HPS, FCS and storage paths remain available. */
-    off = fdt_find_node_offset(&ctx, -1, "leds");
-    if (off >= 0) {
-        ret = fdt_fixup_str(&ctx, off, "leds", "status", "disabled");
+    /* wolfBoot does not program the fabric, so the board config lists the
+     * nodes whose hardware sits behind the unprogrammed FPGA. */
+#ifdef AGILEX5_FDT_DISABLE_PATHS
+    for (i = 0; i < sizeof(agilex5_fdt_disable) /
+                    sizeof(agilex5_fdt_disable[0]); i++) {
+        off = fdt_path_offset(&ctx, agilex5_fdt_disable[i]);
+        if (off < 0)
+            continue;
+        ret = fdt_fixup_str(&ctx, off, agilex5_fdt_disable[i], "status",
+                            "disabled");
         if (ret != 0) {
-            wolfBoot_printf("FDT: failed to disable FPGA LEDs (%d)\n", ret);
+            wolfBoot_printf("FDT: failed to disable %s (%d)\n",
+                agilex5_fdt_disable[i], ret);
             return ret;
         }
     }
+#endif
 
     off = fdt_subnode_offset(&ctx, 0, "chosen");
     if (off == -FDT_ERR_NOTFOUND)

hal/agilex5.h

@@ -51,12 +51,21 @@
 #endif
 
 #define AGILEX5_DDR_BASE       0x80000000UL
-/* The DK-A5E013BM16AEA is fitted with 1792 MiB of LPDDR4.  The SPL/U-Boot
- * device tree normally fills this in at runtime; wolfBoot hands the DTB
- * directly to Linux, so the fixed board size must be supplied here. */
+/* U-Boot normally writes the measured DDR size into the DTB; wolfBoot hands
+ * the DTB straight to Linux, so the board config supplies it. Default is the
+ * DK-A5E013BM16AEA's 1792 MiB. */
+#ifndef AGILEX5_DDR_SIZE
 #define AGILEX5_DDR_SIZE       0x70000000UL
-#define AGILEX5_UART0_BASE     0x10C02000UL
-#define AGILEX5_UART1_BASE     0x10C02100UL
+#endif
+
+/* No UL suffix: the base is also stringified into the earlycon argument. */
+#ifndef DEBUG_UART_BASE
+    #if defined(DEBUG_UART_NUM) && DEBUG_UART_NUM == 1
+        #define DEBUG_UART_BASE 0x10C02100
+    #else
+        #define DEBUG_UART_BASE 0x10C02000
+    #endif
+#endif
 #define AGILEX5_SDHCI_BASE     0x10808000UL
 #define CACHE_LINE_SIZE        64UL