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| 1 | +# wolfBoot configuration for AMD Versal - DDR Boot with a high DDR aperture |
| 2 | +# Versal with DDR mapped at 0x400_0000_0000 instead of the default map. |
| 3 | +# |
| 4 | +# PLM -> PSM -> BL31 (EL3) -> wolfBoot (EL2) -> Linux (EL2) |
| 5 | +# |
| 6 | +# Derived from versal_vmk180.config; see that file for the knobs this one |
| 7 | +# does not change. Every address here lives inside the aperture declared by |
| 8 | +# DDR_HIGH_BASE/DDR_HIGH_SIZE. |
| 9 | +# |
| 10 | +# Three things outside this file have to agree with it: the bootgen BIF |
| 11 | +# (wolfboot.elf at WOLFBOOT_ORIGIN, raw DTB at WOLFBOOT_LOAD_DTS_ADDRESS), |
| 12 | +# BL31's PRELOADED_BL33_BASE = WOLFBOOT_ORIGIN, and the FIT ITS using |
| 13 | +# #address-cells = <2>. |
| 14 | + |
| 15 | +ARCH?=AARCH64 |
| 16 | +TARGET?=versal |
| 17 | + |
| 18 | +WOLFBOOT_VERSION?=1 |
| 19 | + |
| 20 | +# ECC-384 with SHA-384 (good balance of security and performance) |
| 21 | +SIGN?=ECC384 |
| 22 | +HASH?=SHA384 |
| 23 | +IMAGE_HEADER_SIZE?=512 |
| 24 | + |
| 25 | +# RSA 4096-bit with SHA3-384 (alternative) |
| 26 | +#SIGN?=RSA4096 |
| 27 | +#HASH?=SHA3 |
| 28 | +#IMAGE_HEADER_SIZE?=1024 |
| 29 | + |
| 30 | +# Debug options |
| 31 | +DEBUG?=1 |
| 32 | +DEBUG_SYMBOLS=1 |
| 33 | +DEBUG_UART=1 |
| 34 | + |
| 35 | +# Boot Benchmarking (optional): |
| 36 | +# Enables timing of boot operations (flash read, integrity, signature). |
| 37 | +BOOT_BENCHMARK?=1 |
| 38 | + |
| 39 | +VTOR?=1 |
| 40 | +CORTEX_M0?=0 |
| 41 | +NO_ASM?=0 |
| 42 | +ALLOW_DOWNGRADE?=0 |
| 43 | +NVM_FLASH_WRITEONCE?=0 |
| 44 | +V?=0 |
| 45 | +SPMATH?=1 |
| 46 | +RAM_CODE?=0 |
| 47 | +DUALBANK_SWAP?=0 |
| 48 | +PKA?=0 |
| 49 | +WOLFTPM?=0 |
| 50 | + |
| 51 | +# Flash configuration |
| 52 | +EXT_FLASH?=1 |
| 53 | +NO_XIP=1 |
| 54 | + |
| 55 | +# Boot Exception Level (mutually exclusive) |
| 56 | +# BOOT_EL1: drop to EL1 via ERET before entering the application. |
| 57 | +# BOOT_EL2: enter the application at the EL2 wolfBoot runs at (default). |
| 58 | +# EL2 is the default: PSCI brings the secondary cores up at EL2, so dropping |
| 59 | +# only the boot core leaves Linux with "CPUs started in inconsistent modes". |
| 60 | +#BOOT_EL1=1 |
| 61 | +#BOOT_EL2=1 |
| 62 | + |
| 63 | +# ELF loading support |
| 64 | +ELF?=1 |
| 65 | + |
| 66 | +# Native gzip decompression for FIT subimages (set GZIP=0 to disable) |
| 67 | +GZIP?=1 |
| 68 | + |
| 69 | +# FIT ramdisk (initramfs) extraction plus the /chosen/linux,initrd-{start,end} |
| 70 | +# fixup. A stock PetaLinux image.ub carries a ramdisk sub-image that a U-Boot |
| 71 | +# "bootm" loads; without this wolfBoot ignores it. |
| 72 | +FIT_RAMDISK?=1 |
| 73 | + |
| 74 | +# WOLFBOOT_LOAD_KERNEL_ADDRESS / WOLFBOOT_LOAD_RAMDISK_ADDRESS override the |
| 75 | +# FIT's own `load`/`entry`, so a FIT built without them boots. Set below. |
| 76 | + |
| 77 | +# Toolchain |
| 78 | +USE_GCC=1 |
| 79 | +CROSS_COMPILE=aarch64-none-elf- |
| 80 | + |
| 81 | +# ============================================================================ |
| 82 | +# Boot Memory Layout |
| 83 | +# ============================================================================ |
| 84 | +# wolfBoot runs from DDR inside the high aperture, at EL2 non-secure. |
| 85 | +# WOLFBOOT_ORIGIN is set with the rest of the layout further down. |
| 86 | + |
| 87 | +# Optional debugging with OCRAM |
| 88 | +# Versal Gen 1 (VMK180): OCM is 256KB at 0xFFFC0000 - 0xFFFFFFFF |
| 89 | +# Versal Gen 2: OCM is 2MB at 0xFFE00000 - 0xFFFFFFFF |
| 90 | +#WOLFBOOT_ORIGIN=0xFFFC0000 |
| 91 | + |
| 92 | +# Flash Sector Size (QSPI) |
| 93 | +WOLFBOOT_SECTOR_SIZE=0x20000 |
| 94 | + |
| 95 | +# Application Partition Size (44MB) |
| 96 | +WOLFBOOT_PARTITION_SIZE=0x2C00000 |
| 97 | + |
| 98 | +# Location in Flash for Primary Boot Partition |
| 99 | +WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x800000 |
| 100 | + |
| 101 | +# Load Partition to RAM Address (Linux kernel loads here) |
| 102 | +WOLFBOOT_LOAD_ADDRESS?=0x10000000 |
| 103 | + |
| 104 | +# Location in Flash for Secondary Partition (update image) |
| 105 | +WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x3400000 |
| 106 | + |
| 107 | +# Location to store wolfBoot state/swap |
| 108 | +WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x6000000 |
| 109 | + |
| 110 | +# DTS (Device Tree) - matches addresses from BOOT.BIN analysis |
| 111 | +WOLFBOOT_LOAD_DTS_ADDRESS?=0x1000 |
| 112 | + |
| 113 | +# The aperture itself. Base and size are 512 GB aligned with no UL/ULL |
| 114 | +# suffix - the assembler consumes them. NO_DDR_LOW drops the low mapping. |
| 115 | +DDR_HIGH_BASE=0x40000000000 |
| 116 | +DDR_HIGH_SIZE=0x10000000000 |
| 117 | +NO_DDR_LOW=1 |
| 118 | + |
| 119 | +# DDR layout inside the aperture, using '=' to override the '?=' defaults |
| 120 | +# above. Each region is distinct: the kernel and ramdisk destinations must |
| 121 | +# clear the FIT staging buffer the sub-images are read out of. |
| 122 | +# |
| 123 | +# 0x400_0000_1000 DTB (WOLFBOOT_LOAD_DTS_ADDRESS) |
| 124 | +# 0x400_0080_0000 wolfBoot (WOLFBOOT_ORIGIN) |
| 125 | +# 0x400_0200_0000 kernel (WOLFBOOT_LOAD_KERNEL_ADDRESS) |
| 126 | +# 0x400_1000_0000 FIT staging (WOLFBOOT_LOAD_ADDRESS) |
| 127 | +# 0x400_3000_0000 ramdisk (WOLFBOOT_LOAD_RAMDISK_ADDRESS) |
| 128 | +WOLFBOOT_ORIGIN=0x40000800000 |
| 129 | +WOLFBOOT_LOAD_DTS_ADDRESS=0x40000001000 |
| 130 | +WOLFBOOT_LOAD_KERNEL_ADDRESS=0x40002000000 |
| 131 | +WOLFBOOT_LOAD_ADDRESS=0x40010000000 |
| 132 | +WOLFBOOT_LOAD_RAMDISK_ADDRESS=0x40030000000 |
| 133 | + |
| 134 | +# Cap the decompressed kernel at the 224 MB gap to the staging buffer above, |
| 135 | +# which is tighter than the 256 MB WOLFBOOT_FIT_MAX_DECOMP default. |
| 136 | +CFLAGS_EXTRA+=-DWOLFBOOT_FIT_MAX_KERNEL=0xE000000 |
| 137 | +WOLFBOOT_DTS_BOOT_ADDRESS?=0x7B0000 |
| 138 | +WOLFBOOT_DTS_UPDATE_ADDRESS?=0x39B0000 |
| 139 | + |
| 140 | +# Speed up reads by using larger blocks |
| 141 | +CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096 |
| 142 | + |
| 143 | +# UART Configuration - UART0 for APU console |
| 144 | +CFLAGS_EXTRA+=-DDEBUG_UART_NUM=0 |
| 145 | + |
| 146 | +# QSPI Reference Clock: Ref (300MHz default for Versal) |
| 147 | +#CFLAGS_EXTRA+=-DGQSPI_CLK_REF=300000000 |
| 148 | + |
| 149 | +# QSPI Bus Divisor: (2 << div) = BUS (0=div2, 1=div4, 2=div8) |
| 150 | +# MT25QU01G max: 133MHz Quad Read (0x6C) with 8 dummy cycles |
| 151 | +# div=0: 300MHz/2 = 150MHz (above spec but tested working) |
| 152 | +# div=1: 300MHz/4 = 75MHz (within spec, default) |
| 153 | +# div=2: 300MHz/8 = 37.5MHz (conservative) |
| 154 | +#CFLAGS_EXTRA+=-DGQSPI_CLK_DIV=1 |
| 155 | + |
| 156 | +# QSPI flash options (uncomment to enable) |
| 157 | +#CFLAGS_EXTRA+=-DDEBUG_QSPI # Enable QSPI debug logging |
| 158 | +#CFLAGS_EXTRA+=-DGQSPI_MODE_IO # Use polling instead of DMA (slower) |
| 159 | +#CFLAGS_EXTRA+=-DTEST_EXT_FLASH # Run flash erase/write/read test |
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